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authorTristan Gingold <tgingold@free.fr>2018-09-18 04:47:50 +0200
committerTristan Gingold <tgingold@free.fr>2018-09-18 04:47:50 +0200
commiteb9974cf1578e1bd4f4c167601fa767398db3e80 (patch)
treea6c7c8287fadc0af3036ea80fae1ab1bbda1e494 /src/vhdl/translate
parent358f0a800e3b3836e96606ff444df80964f31909 (diff)
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translate: for alias of signal slice: trsnslate name subtype.
Fix #649
Diffstat (limited to 'src/vhdl/translate')
-rw-r--r--src/vhdl/translate/trans-chap3.adb12
-rw-r--r--src/vhdl/translate/trans-chap3.ads5
-rw-r--r--src/vhdl/translate/trans-chap4.adb26
3 files changed, 43 insertions, 0 deletions
diff --git a/src/vhdl/translate/trans-chap3.adb b/src/vhdl/translate/trans-chap3.adb
index fb7a53aeb..ced7e1a94 100644
--- a/src/vhdl/translate/trans-chap3.adb
+++ b/src/vhdl/translate/trans-chap3.adb
@@ -3203,6 +3203,18 @@ package body Trans.Chap3 is
Tinfo.B.Bounds_Ptr_Type));
end Allocate_Unbounded_Composite_Bounds;
+ procedure Translate_Array_Subtype (Arr_Type : Iir) is
+ begin
+ Chap3.Translate_Subtype_Definition
+ (Arr_Type, Get_Base_Type (Arr_Type), False);
+ Chap3.Create_Composite_Subtype_Bounds_Var (Arr_Type, False);
+ end Translate_Array_Subtype;
+
+ procedure Elab_Array_Subtype (Arr_Type : Iir) is
+ begin
+ Chap3.Elab_Composite_Subtype_Bounds (Arr_Type);
+ end Elab_Array_Subtype;
+
procedure Create_Array_Subtype (Sub_Type : Iir)
is
Mark : Id_Mark_Type;
diff --git a/src/vhdl/translate/trans-chap3.ads b/src/vhdl/translate/trans-chap3.ads
index daed65d93..9900f48a9 100644
--- a/src/vhdl/translate/trans-chap3.ads
+++ b/src/vhdl/translate/trans-chap3.ads
@@ -265,6 +265,11 @@ package Trans.Chap3 is
Res : Mnode;
Obj_Type : Iir);
+ -- Used for alias: create the vars for the subtype of the name (when the
+ -- name is a slice). The identifier prefix must have been set.
+ procedure Translate_Array_Subtype (Arr_Type : Iir);
+ procedure Elab_Array_Subtype (Arr_Type : Iir);
+
-- Create the bounds for SUB_TYPE.
-- SUB_TYPE is expected to be a non-static, anonymous array type.
procedure Create_Array_Subtype (Sub_Type : Iir);
diff --git a/src/vhdl/translate/trans-chap4.adb b/src/vhdl/translate/trans-chap4.adb
index b2011df12..47b9f5674 100644
--- a/src/vhdl/translate/trans-chap4.adb
+++ b/src/vhdl/translate/trans-chap4.adb
@@ -1537,6 +1537,7 @@ package body Trans.Chap4 is
(Decl : Iir_Object_Alias_Declaration)
is
Decl_Type : constant Iir := Get_Type (Decl);
+ Name : constant Iir := Get_Name (Decl);
Info : Alias_Info_Acc;
Tinfo : Type_Info_Acc;
Atype : O_Tnode;
@@ -1583,6 +1584,24 @@ package body Trans.Chap4 is
end if;
Info.Alias_Var (Mode) := Create_Var (Id, Atype);
end loop;
+
+ if Get_Kind (Name) = Iir_Kind_Slice_Name
+ and then Info.Alias_Kind = Mode_Signal
+ then
+ -- The name subtype will be evaluated once at elaboration, as it is
+ -- needed when direct drivers are used (in that case, the name is
+ -- evaluated once again).
+ declare
+ Name_Type : constant Iir := Get_Type (Name);
+ Mark1, Mark2 : Id_Mark_Type;
+ begin
+ Push_Identifier_Prefix (Mark1, Get_Identifier (Decl));
+ Push_Identifier_Prefix (Mark2, "AT");
+ Chap3.Translate_Array_Subtype (Name_Type);
+ Pop_Identifier_Prefix (Mark2);
+ Pop_Identifier_Prefix (Mark1);
+ end;
+ end if;
end Translate_Object_Alias_Declaration;
procedure Elab_Object_Alias_Declaration
@@ -1601,6 +1620,13 @@ package body Trans.Chap4 is
Open_Temp;
+ if Get_Kind (Name) = Iir_Kind_Slice_Name
+ and then Alias_Info.Alias_Kind = Mode_Signal
+ then
+ -- See Translate_Object_Alias_Declaration.
+ Chap3.Elab_Array_Subtype (Name_Type);
+ end if;
+
case Alias_Info.Alias_Kind is
when Mode_Value =>
Name_Node (Mode_Value) := Chap6.Translate_Name (Name, Mode_Value);