vhdl: improve support of AMS-vhdl (array and record natures, source quantities)

5 files changed, 10 insertions, 6 deletions

diff --git a/src/vhdl/translate/trans-chap2.adb b/src/vhdl/translate/trans-chap2.adb
index 5cbf85e62..ac58068af 100644
--- a/src/vhdl/translate/trans-chap2.adb
+++ b/src/vhdl/translate/trans-chap2.adb
@@ -114,6 +114,8 @@ package body Trans.Chap2 is
                Mech := Pass_By_Address;
             end if;
             Info.Interface_Mechanism (Mode_Value) := Mech;
+         when Iir_Kind_Interface_Quantity_Declaration =>
+            raise Internal_Error;
       end case;
    end Translate_Interface_Mechanism;
 
diff --git a/src/vhdl/translate/trans-chap5.adb b/src/vhdl/translate/trans-chap5.adb
index 6f4537432..82518576f 100644
--- a/src/vhdl/translate/trans-chap5.adb
+++ b/src/vhdl/translate/trans-chap5.adb
@@ -629,7 +629,7 @@ package body Trans.Chap5 is
       Act_Node : Mnode;
    begin
       Open_Temp;
-      case Iir_Kinds_Association_Element (Get_Kind (Assoc)) is
+      case Iir_Kinds_Association_Element_Parameters (Get_Kind (Assoc)) is
          when Iir_Kind_Association_Element_By_Expression =>
             pragma Assert (Get_Whole_Association_Flag (Assoc));
             Bounds := Get_Unconstrained_Port_Bounds (Assoc, Port);
@@ -704,7 +704,7 @@ package body Trans.Chap5 is
             --  Allocate storage of ports.
             --  (Only once for each port, individual association are ignored).
             Open_Temp;
-            case Iir_Kinds_Association_Element (Get_Kind (Assoc)) is
+            case Iir_Kinds_Association_Element_Parameters (Get_Kind (Assoc)) is
                when Iir_Kind_Association_Element_By_Individual
                  | Iir_Kind_Association_Element_Open =>
                   pragma Assert (Get_Whole_Association_Flag (Assoc));
@@ -719,7 +719,7 @@ package body Trans.Chap5 is
 
             --  Create or copy signals.
             Open_Temp;
-            case Iir_Kinds_Association_Element (Get_Kind (Assoc)) is
+            case Iir_Kinds_Association_Element_Parameters (Get_Kind (Assoc)) is
                when Iir_Kind_Association_Element_By_Expression =>
                   if Get_Whole_Association_Flag (Assoc) then
                      if Get_Collapse_Signal_Flag (Assoc) then
diff --git a/src/vhdl/translate/trans-chap7.adb b/src/vhdl/translate/trans-chap7.adb
index 4d6f68fdc..58d63ce90 100644
--- a/src/vhdl/translate/trans-chap7.adb
+++ b/src/vhdl/translate/trans-chap7.adb
@@ -6248,7 +6248,8 @@ package body Trans.Chap7 is
             | Iir_Predefined_Std_Ulogic_Array_Match_Inequality =>
             null;
 
-         when Iir_Predefined_Now_Function =>
+         when Iir_Predefined_Now_Function
+           | Iir_Predefined_Real_Now_Function =>
             null;
 
             --  when others =>
diff --git a/src/vhdl/translate/trans-chap8.adb b/src/vhdl/translate/trans-chap8.adb
index 521e639e7..00faaa0da 100644
--- a/src/vhdl/translate/trans-chap8.adb
+++ b/src/vhdl/translate/trans-chap8.adb
@@ -2397,7 +2397,7 @@ package body Trans.Chap8 is
             Has_Value_Field := False;
             Has_Ref_Field := False;
 
-            case Iir_Kinds_Association_Element (Get_Kind (Assoc)) is
+            case Iir_Kinds_Association_Element_Parameters (Get_Kind (Assoc)) is
                when Iir_Kind_Association_Element_By_Individual =>
                   --  Create a field for the whole formal.
                   Has_Value_Field := True;
diff --git a/src/vhdl/translate/trans_analyzes.adb b/src/vhdl/translate/trans_analyzes.adb
index 420d04c37..fe16b65fd 100644
--- a/src/vhdl/translate/trans_analyzes.adb
+++ b/src/vhdl/translate/trans_analyzes.adb
@@ -170,7 +170,8 @@ package body Trans_Analyzes is
            | Iir_Kind_For_Loop_Statement
            | Iir_Kind_While_Loop_Statement
            | Iir_Kind_Case_Statement
-           | Iir_Kind_If_Statement =>
+           | Iir_Kind_If_Statement
+           | Iir_Kind_Break_Statement =>
             null;
       end case;
       return Walk_Continue;