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authorTristan Gingold <tgingold@free.fr>2021-05-16 10:04:23 +0200
committerTristan Gingold <tgingold@free.fr>2021-05-16 10:04:23 +0200
commit919645ce03bacb136318ac96ddf920dfc267eeeb (patch)
treeaac18df943b158f5e2ae2811ed79cd500c434199 /src/vhdl/translate
parentc2b3f93dfa40ee92de53b54e38e1819cfc33cb04 (diff)
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trans-chap4: add comments
Diffstat (limited to 'src/vhdl/translate')
-rw-r--r--src/vhdl/translate/trans-chap4.adb4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/vhdl/translate/trans-chap4.adb b/src/vhdl/translate/trans-chap4.adb
index 37ca1646b..5a412dd08 100644
--- a/src/vhdl/translate/trans-chap4.adb
+++ b/src/vhdl/translate/trans-chap4.adb
@@ -2864,6 +2864,7 @@ package body Trans.Chap4 is
(El_List, Conv_Info.Instance_Field, Wki_Instance,
Block_Info.Block_Decls_Ptr_Type);
+ -- Add instance field for the entity in case of direct instantiation.
if Entity /= Null_Iir then
Conv_Info.Instantiated_Entity := Entity;
Entity_Info := Get_Info (Entity);
@@ -3137,6 +3138,9 @@ package body Trans.Chap4 is
end loop;
end Translate_Association_Subprograms;
+ -- Register conversion CONV in association between SIG_IN and SIG_OUT.
+ -- This procedure allocates a record data (described by INFO), fill it
+ -- with addresses of signals and register it to REG_SUBPRG.
procedure Elab_Conversion (Sig_In : Iir;
Sig_Out : Iir;
Conv : Iir;