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| author | Tristan Gingold <tgingold@free.fr> | 2017-04-27 04:45:49 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2017-05-09 21:16:25 +0200 |
| commit | c00e693a478890068c90804e0e64d79f14f5c2aa (patch) | |
| tree | c1934ca103d954124a74d379b8e61e9ada8fdffd /src/vhdl/translate/trans_decls.ads | |
| parent | 47b7ace6a702830d33fb1a26bc49e9362147aa4b (diff) | |
| download | ghdl-c00e693a478890068c90804e0e64d79f14f5c2aa.tar.gz ghdl-c00e693a478890068c90804e0e64d79f14f5c2aa.tar.bz2 ghdl-c00e693a478890068c90804e0e64d79f14f5c2aa.zip | |
Create default value for ports.
Fix #328
Diffstat (limited to 'src/vhdl/translate/trans_decls.ads')
| -rw-r--r-- | src/vhdl/translate/trans_decls.ads | 32 |
1 files changed, 19 insertions, 13 deletions
diff --git a/src/vhdl/translate/trans_decls.ads b/src/vhdl/translate/trans_decls.ads index e8039fc29..0a2d5e69f 100644 --- a/src/vhdl/translate/trans_decls.ads +++ b/src/vhdl/translate/trans_decls.ads @@ -77,52 +77,58 @@ package Trans_Decls is Ghdl_Signal_Start_Assign_Null : O_Dnode; Ghdl_Signal_Next_Assign_Null : O_Dnode; + Ghdl_Create_Signal_B1 : O_Dnode; + Ghdl_Signal_Simple_Assign_B1 : O_Dnode; + Ghdl_Signal_Start_Assign_B1 : O_Dnode; + Ghdl_Signal_Next_Assign_B1 : O_Dnode; + Ghdl_Signal_Associate_B1 : O_Dnode; + Ghdl_Signal_Add_Port_Driver_B1 : O_Dnode; + Ghdl_Signal_Init_B1 : O_Dnode; + Ghdl_Signal_Driving_Value_B1 : O_Dnode; + Ghdl_Create_Signal_E8 : O_Dnode; - Ghdl_Signal_Init_E8 : O_Dnode; Ghdl_Signal_Simple_Assign_E8 : O_Dnode; Ghdl_Signal_Start_Assign_E8 : O_Dnode; Ghdl_Signal_Next_Assign_E8 : O_Dnode; Ghdl_Signal_Associate_E8 : O_Dnode; + Ghdl_Signal_Add_Port_Driver_E8 : O_Dnode; + Ghdl_Signal_Init_E8 : O_Dnode; Ghdl_Signal_Driving_Value_E8 : O_Dnode; Ghdl_Create_Signal_E32 : O_Dnode; - Ghdl_Signal_Init_E32 : O_Dnode; Ghdl_Signal_Simple_Assign_E32 : O_Dnode; Ghdl_Signal_Start_Assign_E32 : O_Dnode; Ghdl_Signal_Next_Assign_E32 : O_Dnode; Ghdl_Signal_Associate_E32 : O_Dnode; + Ghdl_Signal_Add_Port_Driver_E32 : O_Dnode; + Ghdl_Signal_Init_E32 : O_Dnode; Ghdl_Signal_Driving_Value_E32 : O_Dnode; - Ghdl_Create_Signal_B1 : O_Dnode; - Ghdl_Signal_Init_B1 : O_Dnode; - Ghdl_Signal_Simple_Assign_B1 : O_Dnode; - Ghdl_Signal_Start_Assign_B1 : O_Dnode; - Ghdl_Signal_Next_Assign_B1 : O_Dnode; - Ghdl_Signal_Associate_B1 : O_Dnode; - Ghdl_Signal_Driving_Value_B1 : O_Dnode; - Ghdl_Create_Signal_I32 : O_Dnode; - Ghdl_Signal_Init_I32 : O_Dnode; Ghdl_Signal_Simple_Assign_I32 : O_Dnode; Ghdl_Signal_Start_Assign_I32 : O_Dnode; Ghdl_Signal_Next_Assign_I32 : O_Dnode; Ghdl_Signal_Associate_I32 : O_Dnode; + Ghdl_Signal_Add_Port_Driver_I32 : O_Dnode; + Ghdl_Signal_Init_I32 : O_Dnode; Ghdl_Signal_Driving_Value_I32 : O_Dnode; Ghdl_Create_Signal_F64 : O_Dnode; - Ghdl_Signal_Init_F64 : O_Dnode; Ghdl_Signal_Simple_Assign_F64 : O_Dnode; Ghdl_Signal_Start_Assign_F64 : O_Dnode; Ghdl_Signal_Next_Assign_F64 : O_Dnode; Ghdl_Signal_Associate_F64 : O_Dnode; + Ghdl_Signal_Add_Port_Driver_F64 : O_Dnode; + Ghdl_Signal_Init_F64 : O_Dnode; Ghdl_Signal_Driving_Value_F64 : O_Dnode; Ghdl_Create_Signal_I64 : O_Dnode; - Ghdl_Signal_Init_I64 : O_Dnode; Ghdl_Signal_Simple_Assign_I64 : O_Dnode; Ghdl_Signal_Start_Assign_I64 : O_Dnode; Ghdl_Signal_Next_Assign_I64 : O_Dnode; Ghdl_Signal_Associate_I64 : O_Dnode; + Ghdl_Signal_Add_Port_Driver_I64 : O_Dnode; + Ghdl_Signal_Init_I64 : O_Dnode; Ghdl_Signal_Driving_Value_I64 : O_Dnode; Ghdl_Signal_In_Conversion : O_Dnode; |