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authorTristan Gingold <tgingold@free.fr>2019-04-27 10:14:26 +0200
committerTristan Gingold <tgingold@free.fr>2019-04-27 10:21:30 +0200
commite857941acd16e3a678296b26e34b4bf330d5239c (patch)
treeb0cd38523d2ee9509088aadcfe0c33bc5ec0b9a4 /src/vhdl/translate/trans-chap12.ads
parentc9174bea8a486faf265feae222593d4553572d7d (diff)
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vhdl: supports VHPIDIRECT in mcode backend.
src: add hash.ad[sb], interning.ad[sb] Automatically link with vhpidirect libraries.
Diffstat (limited to 'src/vhdl/translate/trans-chap12.ads')
-rw-r--r--src/vhdl/translate/trans-chap12.ads7
1 files changed, 1 insertions, 6 deletions
diff --git a/src/vhdl/translate/trans-chap12.ads b/src/vhdl/translate/trans-chap12.ads
index a0db62399..248b7851d 100644
--- a/src/vhdl/translate/trans-chap12.ads
+++ b/src/vhdl/translate/trans-chap12.ads
@@ -23,11 +23,6 @@ package Trans.Chap12 is
-- Generate ortho code to elaborate declaration of the top unit.
procedure Call_Elab_Decls (Arch : Iir; Arch_Instance : O_Enode);
- -- Write to file FILELIST all the files that are needed to link the design.
- procedure Write_File_List (Filelist : String);
-
-- Generate elaboration code for CONFIG.
- procedure Elaborate (Config : Iir_Design_Unit;
- Filelist : String;
- Whole : Boolean);
+ procedure Elaborate (Config : Iir_Design_Unit; Whole : Boolean);
end Trans.Chap12;