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authorTristan Gingold <tgingold@free.fr>2017-12-05 18:35:17 +0100
committerTristan Gingold <tgingold@free.fr>2017-12-05 18:35:17 +0100
commit83f07243e90f7fd60516738f42a79d9f7cc01736 (patch)
tree8637543f5519d04cdee917ccc44f7908f311713c /src/vhdl/simulate
parent18b19a5c8e99f1e0b562eafb95869cfe4cca8ceb (diff)
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simul: fix elaboration check for package.
Diffstat (limited to 'src/vhdl/simulate')
-rw-r--r--src/vhdl/simulate/simul-elaboration.adb6
1 files changed, 5 insertions, 1 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.adb b/src/vhdl/simulate/simul-elaboration.adb
index 55e40bfa9..7547b3782 100644
--- a/src/vhdl/simulate/simul-elaboration.adb
+++ b/src/vhdl/simulate/simul-elaboration.adb
@@ -379,10 +379,14 @@ package body Simul.Elaboration is
Package_Info : constant Sim_Info_Acc := Get_Info (Decl);
Instance : Block_Instance_Acc;
begin
+ if Block /= Global_Instances then
+ -- Packages in library unit can be elaborated in a different order.
+ Create_Object (Block, Package_Info.Pkg_Slot);
+ end if;
+
Instance := Create_Block_Instance (Block, Decl, Decl);
pragma Assert (Block.Block_Scope = Package_Info.Pkg_Parent);
- pragma Assert (Block.Objects (Package_Info.Pkg_Slot) = null);
Block.Objects (Package_Info.Pkg_Slot) :=
Create_Instance_Value (Instance);