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author | Tristan Gingold <tgingold@free.fr> | 2017-12-03 10:27:57 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2017-12-03 10:27:57 +0100 |
commit | e62abb62264f7271ad5521d75a84fd689c3b49e0 (patch) | |
tree | e3a14524a135b4dad09f3b0833d77ef474fe601a /src/vhdl/simulate/simul-elaboration.ads | |
parent | 2b61f516ef9775502da6dfcc8b21e79cf8482c87 (diff) | |
download | ghdl-e62abb62264f7271ad5521d75a84fd689c3b49e0.tar.gz ghdl-e62abb62264f7271ad5521d75a84fd689c3b49e0.tar.bz2 ghdl-e62abb62264f7271ad5521d75a84fd689c3b49e0.zip |
simul: refactoring: scope is now the corresponding sim_info.
Diffstat (limited to 'src/vhdl/simulate/simul-elaboration.ads')
-rw-r--r-- | src/vhdl/simulate/simul-elaboration.ads | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/src/vhdl/simulate/simul-elaboration.ads b/src/vhdl/simulate/simul-elaboration.ads index 07969719f..a469ead00 100644 --- a/src/vhdl/simulate/simul-elaboration.ads +++ b/src/vhdl/simulate/simul-elaboration.ads @@ -21,7 +21,6 @@ with Types; use Types; with Iirs; use Iirs; with Simul.Environments; use Simul.Environments; with Grt.Types; use Grt.Types; -with Simul.Annotations; use Simul.Annotations; -- This package elaborates design hierarchy. |