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| author | Tristan Gingold <gingold@adacore.com> | 2015-12-19 21:36:47 +0100 |
|---|---|---|
| committer | Tristan Gingold <gingold@adacore.com> | 2015-12-19 21:36:47 +0100 |
| commit | ae7a913a9c8193daee80f6774e8cb7351edea974 (patch) | |
| tree | 620864a61a70d1d490665a511309e37e2250060f /src/vhdl/simulate/elaboration.ads | |
| parent | 7fc250bfc464604ba811e9785a4719ac2c0e6564 (diff) | |
| download | ghdl-ae7a913a9c8193daee80f6774e8cb7351edea974.tar.gz ghdl-ae7a913a9c8193daee80f6774e8cb7351edea974.tar.bz2 ghdl-ae7a913a9c8193daee80f6774e8cb7351edea974.zip | |
Adjust simulation after sigptr changes.
Diffstat (limited to 'src/vhdl/simulate/elaboration.ads')
| -rw-r--r-- | src/vhdl/simulate/elaboration.ads | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/vhdl/simulate/elaboration.ads b/src/vhdl/simulate/elaboration.ads index e20382668..ff8b2109f 100644 --- a/src/vhdl/simulate/elaboration.ads +++ b/src/vhdl/simulate/elaboration.ads @@ -174,10 +174,11 @@ package Elaboration is type Signal_Entry (Kind : Signal_Type_Kind := User_Signal) is record Decl : Iir; Sig : Iir_Value_Literal_Acc; + Val : Iir_Value_Literal_Acc; Instance : Block_Instance_Acc; case Kind is when User_Signal => - Init : Iir_Value_Literal_Acc; + null; when Implicit_Quiet | Implicit_Stable | Implicit_Delayed | Implicit_Transaction => Time : Grt.Types.Ghdl_I64; |