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author | Tristan Gingold <tgingold@free.fr> | 2020-03-31 07:34:25 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2020-03-31 18:29:05 +0200 |
commit | d8afbddcf37ea68a19b6edfa4820ef3bdd0c5076 (patch) | |
tree | b51452cd7023564f5500c8b61a26c568dead732f /src/types.ads | |
parent | 5aa87ef99e4f5ba046d215ac6d99a645ce7a0e1d (diff) | |
download | ghdl-d8afbddcf37ea68a19b6edfa4820ef3bdd0c5076.tar.gz ghdl-d8afbddcf37ea68a19b6edfa4820ef3bdd0c5076.tar.bz2 ghdl-d8afbddcf37ea68a19b6edfa4820ef3bdd0c5076.zip |
synth: preliminary work to export module parameters.
Diffstat (limited to 'src/types.ads')
-rw-r--r-- | src/types.ads | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/types.ads b/src/types.ads index bd63f3b87..af62cbe34 100644 --- a/src/types.ads +++ b/src/types.ads @@ -44,6 +44,16 @@ package Types is type Fp64 is new Interfaces.IEEE_Float_64; type Fp32 is new Interfaces.IEEE_Float_32; + -- The verilog logic type (when used in a vector). + -- Coding of 01zx: + -- For 0 and 1, ZX is 0, VAL is the bit value. + -- For z: ZX is 1, VAL is 0. + -- For x: ZX is 1, VAL is 1. + type Logic_32 is record + Val : Uns32; -- AKA aval + Zx : Uns32; -- AKA bval + end record; + -- Useful types. type String_Acc is access String; type String_Cst is access constant String; |