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| author | Tristan Gingold <tgingold@free.fr> | 2019-12-31 18:56:23 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-12-31 18:57:44 +0100 |
| commit | d17750101d69d9113ffab6792c74ce1567d6002a (patch) | |
| tree | 8c3791dd7b1bdce85002a60b09f395de9203c392 /src/synth | |
| parent | 3485a2054df425a54796ce69f28d19b6eea2b868 (diff) | |
| download | ghdl-d17750101d69d9113ffab6792c74ce1567d6002a.tar.gz ghdl-d17750101d69d9113ffab6792c74ce1567d6002a.tar.bz2 ghdl-d17750101d69d9113ffab6792c74ce1567d6002a.zip | |
synth-inference: merge reset for sub-nets.
For tgingold/ghdlsynth-beta#76
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-inference.adb | 17 |
1 files changed, 16 insertions, 1 deletions
diff --git a/src/synth/synth-inference.adb b/src/synth/synth-inference.adb index 270c944fa..db16147df 100644 --- a/src/synth/synth-inference.adb +++ b/src/synth/synth-inference.adb @@ -324,6 +324,21 @@ package body Synth.Inference is end if; end Check_FF_Else; + function Is_Prev_FF_Value (V : Net; Prev_Val : Net; Off : Uns32) + return Boolean + is + Inst : Instance; + begin + if V = Prev_Val then + pragma Assert (Off = 0); + return True; + end if; + Inst := Get_Net_Parent (V); + return Get_Id (Inst) = Id_Extract + and then Get_Param_Uns32 (Inst, 0) = Off + and then Get_Input_Net (Inst, 0) = Prev_Val; + end Is_Prev_FF_Value; + -- LAST_MUX is the mux whose input 0 is the loop and clock for selector. procedure Infere_FF (Ctxt : Context_Acc; Wid : Wire_Id; @@ -415,7 +430,7 @@ package body Synth.Inference is Last_Out := Get_Output (Mux, 0); - if Mux_Rst_Val = Prev_Val then + if Is_Prev_FF_Value (Mux_Rst_Val, Prev_Val, Off) then -- The mux is like an enable. Like in this example, q2 is not -- assigned when RST is true: -- if rst then |