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authorTristan Gingold <tgingold@free.fr>2019-09-19 06:21:53 +0200
committerTristan Gingold <tgingold@free.fr>2019-09-19 06:32:17 +0200
commitb93769c93d695b4dc77199bdab041da50b1fb5ff (patch)
tree66186b8e57c53bd7ac5cb3cb1f17c61479a90d3f /src/synth
parentf659edc23a249a35e78956054afed0fdc256d127 (diff)
downloadghdl-b93769c93d695b4dc77199bdab041da50b1fb5ff.tar.gz
ghdl-b93769c93d695b4dc77199bdab041da50b1fb5ff.tar.bz2
ghdl-b93769c93d695b4dc77199bdab041da50b1fb5ff.zip
synth: make synth_instance_type private.
Diffstat (limited to 'src/synth')
-rw-r--r--src/synth/synth-context.adb51
-rw-r--r--src/synth/synth-context.ads62
-rw-r--r--src/synth/synth-decls.adb5
-rw-r--r--src/synth/synth-insts.adb50
-rw-r--r--src/synth/synth-oper.adb39
-rw-r--r--src/synth/synth-stmts.adb32
-rw-r--r--src/synth/synthesis.adb2
7 files changed, 160 insertions, 81 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb
index 8b0b190dc..e89a29e11 100644
--- a/src/synth/synth-context.adb
+++ b/src/synth/synth-context.adb
@@ -38,14 +38,16 @@ package body Synth.Context is
Table_Low_Bound => 1,
Table_Initial => 16);
- function Make_Instance (Parent : Synth_Instance_Acc; Info : Sim_Info_Acc)
+ function Make_Instance (Parent : Synth_Instance_Acc;
+ Info : Sim_Info_Acc;
+ Name : Sname := No_Sname)
return Synth_Instance_Acc
is
Res : Synth_Instance_Acc;
begin
Res := new Synth_Instance_Type'(Max_Objs => Info.Nbr_Objects,
M => No_Module,
- Name => No_Sname,
+ Name => Name,
Block_Scope => Info,
Up_Block => Parent,
Elab_Objects => 0,
@@ -61,6 +63,27 @@ package body Synth.Context is
Deallocate (Synth_Inst);
end Free_Instance;
+ procedure Set_Module (Inst : Synth_Instance_Acc; M : Module) is
+ begin
+ Inst.M := M;
+ end Set_Module;
+
+ function Get_Module (Inst : Synth_Instance_Acc) return Module is
+ begin
+ return Inst.M;
+ end Get_Module;
+
+ function Get_Sname (Inst : Synth_Instance_Acc) return Sname is
+ begin
+ return Inst.Name;
+ end Get_Sname;
+
+ procedure Set_Block_Scope
+ (Inst : Synth_Instance_Acc; Scope : Sim_Info_Acc) is
+ begin
+ Inst.Block_Scope := Scope;
+ end Set_Block_Scope;
+
function Create_Value_Instance (Inst : Synth_Instance_Acc)
return Value_Acc is
begin
@@ -120,15 +143,35 @@ package body Synth.Context is
Syn_Inst.Elab_Objects := Slot + Num - 1;
end Create_Object;
- procedure Create_Object
+ procedure Create_Object_Force
(Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc)
is
Info : constant Sim_Info_Acc := Get_Info (Decl);
begin
- Create_Object (Syn_Inst, Info.Slot, 1);
+ pragma Assert (Syn_Inst.Objects (Info.Slot) = null);
Syn_Inst.Objects (Info.Slot) := Val;
+ end Create_Object_Force;
+
+ procedure Create_Object
+ (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc)
+ is
+ Info : constant Sim_Info_Acc := Get_Info (Decl);
+ begin
+ if Syn_Inst /= Global_Instance then
+ Create_Object (Syn_Inst, Info.Slot, 1);
+ end if;
+ Create_Object_Force (Syn_Inst, Decl, Val);
end Create_Object;
+ procedure Create_Package_Object
+ (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc)
+ is
+ Info : constant Sim_Info_Acc := Get_Info (Decl);
+ begin
+ pragma Assert (Syn_Inst.Objects (Info.Pkg_Slot) = null);
+ Syn_Inst.Objects (Info.Pkg_Slot) := Val;
+ end Create_Package_Object;
+
procedure Destroy_Object
(Syn_Inst : Synth_Instance_Acc; Decl : Iir)
is
diff --git a/src/synth/synth-context.ads b/src/synth/synth-context.ads
index 0cfbc949c..bf729a282 100644
--- a/src/synth/synth-context.ads
+++ b/src/synth/synth-context.ads
@@ -30,28 +30,9 @@ package Synth.Context is
-- Block_Instance_Type.
type Objects_Array is array (Object_Slot_Type range <>) of Value_Acc;
- type Synth_Instance_Type;
+ type Synth_Instance_Type (<>) is private;
type Synth_Instance_Acc is access Synth_Instance_Type;
- type Synth_Instance_Type (Max_Objs : Object_Slot_Type) is record
- -- Module which owns gates created for this instance.
- M : Module;
-
- -- Name prefix for declarations.
- Name : Sname;
-
- -- The corresponding info for this instance.
- Block_Scope : Sim_Info_Acc;
-
- -- Parent instance.
- Up_Block : Synth_Instance_Acc;
-
- Elab_Objects : Object_Slot_Type;
-
- -- Instance for synthesis.
- Objects : Objects_Array (1 .. Max_Objs);
- end record;
-
type Instance_Map_Array is array (Block_Instance_Id range <>)
of Synth_Instance_Acc;
type Instance_Map_Array_Acc is access Instance_Map_Array;
@@ -68,13 +49,33 @@ package Synth.Context is
return Synth_Instance_Acc;
-- Create and free the corresponding synth instance.
- function Make_Instance (Parent : Synth_Instance_Acc; Info : Sim_Info_Acc)
+ function Make_Instance (Parent : Synth_Instance_Acc;
+ Info : Sim_Info_Acc;
+ Name : Sname := No_Sname)
return Synth_Instance_Acc;
procedure Free_Instance (Synth_Inst : in out Synth_Instance_Acc);
+ function Get_Sname (Inst : Synth_Instance_Acc) return Sname;
+ pragma Inline (Get_Sname);
+
+ procedure Set_Module (Inst : Synth_Instance_Acc; M : Module);
+ function Get_Module (Inst : Synth_Instance_Acc) return Module;
+ pragma Inline (Set_Module, Get_Module);
+
+ procedure Set_Block_Scope
+ (Inst : Synth_Instance_Acc; Scope : Sim_Info_Acc);
+
procedure Create_Object
(Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc);
+ procedure Create_Package_Object
+ (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc);
+
+ -- Force the value of DECL, without checking for elaboration order.
+ -- It is for deferred constants.
+ procedure Create_Object_Force
+ (Syn_Inst : Synth_Instance_Acc; Decl : Iir; Val : Value_Acc);
+
procedure Destroy_Object
(Syn_Inst : Synth_Instance_Acc; Decl : Iir);
@@ -97,4 +98,23 @@ package Synth.Context is
function Create_Value_Instance (Inst : Synth_Instance_Acc)
return Value_Acc;
+private
+ type Synth_Instance_Type (Max_Objs : Object_Slot_Type) is record
+ -- Module which owns gates created for this instance.
+ M : Module;
+
+ -- Name prefix for declarations.
+ Name : Sname;
+
+ -- The corresponding info for this instance.
+ Block_Scope : Sim_Info_Acc;
+
+ -- Parent instance.
+ Up_Block : Synth_Instance_Acc;
+
+ Elab_Objects : Object_Slot_Type;
+
+ -- Instance for synthesis.
+ Objects : Objects_Array (1 .. Max_Objs);
+ end record;
end Synth.Context;
diff --git a/src/synth/synth-decls.adb b/src/synth/synth-decls.adb
index eefa30661..f2f7b5d5e 100644
--- a/src/synth/synth-decls.adb
+++ b/src/synth/synth-decls.adb
@@ -27,7 +27,6 @@ with Vhdl.Errors; use Vhdl.Errors;
with Vhdl.Utils; use Vhdl.Utils;
with Vhdl.Std_Package;
with Vhdl.Ieee.Std_Logic_1164;
-with Vhdl.Annotations; use Vhdl.Annotations;
with Synth.Values; use Synth.Values;
with Synth.Environment; use Synth.Environment;
@@ -51,7 +50,7 @@ package body Synth.Decls is
when Value_Wire =>
-- FIXME: get the width directly from the wire ?
W := Get_Type_Width (Val.Typ);
- Name := New_Sname (Syn_Inst.Name, Get_Identifier (Decl));
+ Name := New_Sname (Get_Sname (Syn_Inst), Get_Identifier (Decl));
if Init /= null then
Ival := Get_Net (Init);
pragma Assert (Get_Width (Ival) = W);
@@ -396,7 +395,7 @@ package body Synth.Decls is
if First_Decl /= Null_Node then
Val := Synth_Expression_With_Type
(Syn_Inst, Get_Default_Value (Decl), Get_Type (Decl));
- Syn_Inst.Objects (Get_Info (First_Decl).Slot) := Val;
+ Create_Object_Force (Syn_Inst, First_Decl, Val);
end if;
end Synth_Constant_Declaration;
diff --git a/src/synth/synth-insts.adb b/src/synth/synth-insts.adb
index fc9037095..cc877c929 100644
--- a/src/synth/synth-insts.adb
+++ b/src/synth/synth-insts.adb
@@ -172,9 +172,9 @@ package body Synth.Insts is
end if;
-- Create the instance.
- Syn_Inst := Make_Instance (Global_Instance, Get_Info (Imp));
- Syn_Inst.Block_Scope := Get_Info (Decl);
- Syn_Inst.Name := No_Sname;
+ Syn_Inst := Make_Instance (Global_Instance, Get_Info (Imp), No_Sname);
+ -- Make the entity reachable.
+ Set_Block_Scope (Syn_Inst, Get_Info (Decl));
-- Copy values for generics.
Inter := Get_Generic_Chain (Decl);
@@ -218,9 +218,10 @@ package body Synth.Insts is
end loop;
-- Declare module.
- Syn_Inst.M := New_User_Module
- (Global_Module, New_Sname_User (Get_Identifier (Decl)),
- Id_User_None, Nbr_Inputs, Nbr_Outputs, 0);
+ Set_Module (Syn_Inst,
+ New_User_Module
+ (Global_Module, New_Sname_User (Get_Identifier (Decl)),
+ Id_User_None, Nbr_Inputs, Nbr_Outputs, 0));
-- Add ports to module.
declare
@@ -244,7 +245,7 @@ package body Synth.Insts is
end loop;
pragma Assert (Nbr_Inputs = Inports'Last);
pragma Assert (Nbr_Outputs = Outports'Last);
- Set_Port_Desc (Syn_Inst.M, Inports, Outports);
+ Set_Port_Desc (Get_Module (Syn_Inst), Inports, Outports);
end;
return Inst_Object'(Decl => Decl,
@@ -331,8 +332,8 @@ package body Synth.Insts is
Inst : Instance;
begin
-- Elaborate generic + map aspect
- Sub_Inst := Make_Instance (Syn_Inst, Get_Info (Ent));
- Sub_Inst.Name := New_Sname_User (Get_Identifier (Ent));
+ Sub_Inst := Make_Instance
+ (Syn_Inst, Get_Info (Ent), New_Sname_User (Get_Identifier (Ent)));
Synth_Subprogram_Association (Sub_Inst, Syn_Inst,
Get_Generic_Chain (Ent),
Get_Generic_Map_Aspect_Chain (Stmt));
@@ -369,8 +370,9 @@ package body Synth.Insts is
-- TODO: free sub_inst.
- Inst := New_Instance (Syn_Inst.M, Inst_Obj.Syn_Inst.M,
- New_Sname_User (Get_Identifier (Stmt)));
+ Inst := New_Instance
+ (Get_Module (Syn_Inst), Get_Module (Inst_Obj.Syn_Inst),
+ New_Sname_User (Get_Identifier (Stmt)));
Synth_Instantiate_Module
(Syn_Inst, Inst, Inst_Obj, Get_Port_Map_Aspect_Chain (Stmt));
@@ -458,8 +460,8 @@ package body Synth.Insts is
-- Create the sub-instance for the component
-- Elaborate generic + map aspect
- Comp_Inst := Make_Instance (Syn_Inst, Get_Info (Component));
- Comp_Inst.Name := New_Sname_User (Get_Identifier (Component));
+ Comp_Inst := Make_Instance (Syn_Inst, Get_Info (Component),
+ New_Sname_User (Get_Identifier (Component)));
Synth_Subprogram_Association (Comp_Inst, Syn_Inst,
Get_Generic_Chain (Component),
Get_Generic_Map_Aspect_Chain (Stmt));
@@ -522,8 +524,8 @@ package body Synth.Insts is
end if;
-- Elaborate generic + map aspect
- Sub_Inst := Make_Instance (Comp_Inst, Get_Info (Ent));
- Sub_Inst.Name := New_Sname_User (Get_Identifier (Ent));
+ Sub_Inst := Make_Instance
+ (Comp_Inst, Get_Info (Ent), New_Sname_User (Get_Identifier (Ent)));
Synth_Subprogram_Association (Sub_Inst, Comp_Inst,
Get_Generic_Chain (Ent),
Get_Generic_Map_Aspect_Chain (Bind));
@@ -540,8 +542,9 @@ package body Synth.Insts is
-- TODO: free sub_inst.
- Inst := New_Instance (Syn_Inst.M, Inst_Obj.Syn_Inst.M,
- New_Sname_User (Get_Identifier (Stmt)));
+ Inst := New_Instance
+ (Get_Module (Syn_Inst), Get_Module (Inst_Obj.Syn_Inst),
+ New_Sname_User (Get_Identifier (Stmt)));
Synth_Instantiate_Module
(Comp_Inst, Inst, Inst_Obj, Get_Port_Map_Aspect_Chain (Bind));
@@ -599,9 +602,10 @@ package body Synth.Insts is
Inter : Node;
Inst_Obj : Inst_Object;
begin
- Syn_Inst := Make_Instance (Global_Instance, Get_Info (Arch));
- Syn_Inst.Block_Scope := Get_Info (Entity);
- Syn_Inst.Name := New_Sname_User (Get_Identifier (Entity));
+ Syn_Inst := Make_Instance (Global_Instance, Get_Info (Arch),
+ New_Sname_User (Get_Identifier (Entity)));
+ -- Make the entity visible.
+ Set_Block_Scope (Syn_Inst, Get_Info (Entity));
-- Compute generics.
Inter := Get_Generic_Chain (Entity);
@@ -768,8 +772,8 @@ package body Synth.Insts is
return;
end if;
- Self_Inst := Create_Self_Instance (Syn_Inst.M);
- Builders.Set_Parent (Build_Context, Syn_Inst.M);
+ Self_Inst := Create_Self_Instance (Get_Module (Syn_Inst));
+ Builders.Set_Parent (Build_Context, Get_Module (Syn_Inst));
-- Create wires for inputs and outputs.
Inter := Get_Port_Chain (Entity);
@@ -810,7 +814,7 @@ package body Synth.Insts is
-- a correctness point: there might be some unsynthesizable gates, like
-- the one created for 'rising_egde (clk) and not rst'.
if not Flags.Flag_Debug_Nocleanup then
- Netlists.Utils.Remove_Unused_Instances (Syn_Inst.M);
+ Netlists.Utils.Remove_Unused_Instances (Get_Module (Syn_Inst));
end if;
end Synth_Instance;
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb
index 2327d32d9..a6a7883f3 100644
--- a/src/synth/synth-oper.adb
+++ b/src/synth/synth-oper.adb
@@ -884,6 +884,8 @@ package body Synth.Oper is
Get_Implicit_Definition (Imp);
Assoc_Chain : constant Node := Get_Parameter_Association_Chain (Expr);
Inter_Chain : constant Node := Get_Interface_Declaration_Chain (Imp);
+ Param1 : Node;
+ Param2 : Node;
Subprg_Inst : Synth_Instance_Acc;
M : Areapools.Mark_Type;
begin
@@ -893,11 +895,18 @@ package body Synth.Oper is
Synth_Subprogram_Association
(Subprg_Inst, Syn_Inst, Inter_Chain, Assoc_Chain);
+ Param1 := Inter_Chain;
+ if Param1 /= Null_Node then
+ Param2 := Get_Chain (Inter_Chain);
+ else
+ Param2 := Null_Node;
+ end if;
+
case Def is
when Iir_Predefined_Ieee_Numeric_Std_Touns_Nat_Nat_Uns =>
declare
- Arg : constant Value_Acc := Subprg_Inst.Objects (1);
- Size : constant Value_Acc := Subprg_Inst.Objects (2);
+ Arg : constant Value_Acc := Get_Value (Subprg_Inst, Param1);
+ Size : constant Value_Acc := Get_Value (Subprg_Inst, Param2);
Arg_Net : Net;
begin
if not Is_Const (Size) then
@@ -925,14 +934,14 @@ package body Synth.Oper is
Vhdl.Std_Package.Integer_Subtype_Definition);
begin
return Create_Value_Net
- (Synth_Uresize (Get_Net (Subprg_Inst.Objects (1)),
+ (Synth_Uresize (Get_Net (Get_Value (Subprg_Inst, Param1)),
Int_Type.W, Expr),
Int_Type);
end;
when Iir_Predefined_Ieee_Numeric_Std_Resize_Uns_Nat =>
declare
- V : constant Value_Acc := Subprg_Inst.Objects (1);
- Sz : constant Value_Acc := Subprg_Inst.Objects (2);
+ V : constant Value_Acc := Get_Value (Subprg_Inst, Param1);
+ Sz : constant Value_Acc := Get_Value (Subprg_Inst, Param2);
W : Width;
begin
if not Is_Const (Sz) then
@@ -946,8 +955,8 @@ package body Synth.Oper is
end;
when Iir_Predefined_Ieee_Numeric_Std_Resize_Sgn_Nat =>
declare
- V : constant Value_Acc := Subprg_Inst.Objects (1);
- Sz : constant Value_Acc := Subprg_Inst.Objects (2);
+ V : constant Value_Acc := Get_Value (Subprg_Inst, Param1);
+ Sz : constant Value_Acc := Get_Value (Subprg_Inst, Param2);
W : Width;
begin
if not Is_Const (Sz) then
@@ -961,22 +970,22 @@ package body Synth.Oper is
end;
when Iir_Predefined_Ieee_Numeric_Std_Shl_Uns_Nat =>
declare
- L : constant Value_Acc := Subprg_Inst.Objects (1);
- R : constant Value_Acc := Subprg_Inst.Objects (2);
+ L : constant Value_Acc := Get_Value (Subprg_Inst, Param1);
+ R : constant Value_Acc := Get_Value (Subprg_Inst, Param2);
begin
return Synth_Shift (Id_Lsl, L, R, Expr);
end;
when Iir_Predefined_Ieee_Numeric_Std_Shr_Uns_Nat =>
declare
- L : constant Value_Acc := Subprg_Inst.Objects (1);
- R : constant Value_Acc := Subprg_Inst.Objects (2);
+ L : constant Value_Acc := Get_Value (Subprg_Inst, Param1);
+ R : constant Value_Acc := Get_Value (Subprg_Inst, Param2);
begin
return Synth_Shift (Id_Lsr, L, R, Expr);
end;
when Iir_Predefined_Ieee_Numeric_Std_Match_Suv =>
declare
- L : constant Value_Acc := Subprg_Inst.Objects (1);
- R : constant Value_Acc := Subprg_Inst.Objects (2);
+ L : constant Value_Acc := Get_Value (Subprg_Inst, Param1);
+ R : constant Value_Acc := Get_Value (Subprg_Inst, Param2);
begin
if Is_Const (L) then
return Synth_Std_Match (L, R, Expr);
@@ -990,7 +999,7 @@ package body Synth.Oper is
end;
when Iir_Predefined_Ieee_Math_Real_Log2 =>
declare
- V : constant Value_Acc := Subprg_Inst.Objects (1);
+ V : constant Value_Acc := Get_Value (Subprg_Inst, Param1);
function Log2 (Arg : Fp64) return Fp64;
pragma Import (C, Log2);
@@ -1005,7 +1014,7 @@ package body Synth.Oper is
end;
when Iir_Predefined_Ieee_Math_Real_Ceil =>
declare
- V : constant Value_Acc := Subprg_Inst.Objects (1);
+ V : constant Value_Acc := Get_Value (Subprg_Inst, Param1);
function Ceil (Arg : Fp64) return Fp64;
pragma Import (C, Ceil);
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb
index 03f6d06e9..b85c77f12 100644
--- a/src/synth/synth-stmts.adb
+++ b/src/synth/synth-stmts.adb
@@ -1213,6 +1213,7 @@ package body Synth.Stmts is
Subprg_Body : constant Node := Get_Subprogram_Body (Imp);
Decls_Chain : constant Node := Get_Declaration_Chain (Subprg_Body);
Sub_C : Seq_Context;
+ Sub_Sname : Sname;
M : Areapools.Mark_Type;
begin
if Get_Implicit_Definition (Imp) in Iir_Predefined_Implicit then
@@ -1224,7 +1225,8 @@ package body Synth.Stmts is
end if;
Areapools.Mark (M, Instance_Pool.all);
- Sub_C.Inst := Make_Instance (C.Inst, Get_Info (Imp));
+ Sub_Sname := New_Sname (Get_Sname (C.Inst), Get_Identifier (Imp));
+ Sub_C.Inst := Make_Instance (C.Inst, Get_Info (Imp), Sub_Sname);
Synth_Subprogram_Association
(Sub_C.Inst, C.Inst, Inter_Chain, Assoc_Chain);
@@ -1232,7 +1234,6 @@ package body Synth.Stmts is
Synth_Declarations (Sub_C.Inst, Decls_Chain);
if Is_Valid (Decls_Chain) then
- Sub_C.Inst.Name := New_Sname (C.Inst.Name, Get_Identifier (Imp));
Synth_Declarations (Sub_C.Inst, Decls_Chain);
end if;
@@ -1425,9 +1426,15 @@ package body Synth.Stmts is
Decls_Chain : constant Node := Get_Declaration_Chain (Proc);
Prev_Instance_Pool : constant Areapool_Acc := Instance_Pool;
M : Areapools.Mark_Type;
+ C_Sname : Sname;
C : Seq_Context;
begin
- C := (Inst => Make_Instance (Syn_Inst, Info),
+ if Label = Null_Identifier then
+ C_Sname := New_Internal_Name (Build_Context, Get_Sname (Syn_Inst));
+ else
+ C_Sname := New_Sname (Get_Sname (Syn_Inst), Label);
+ end if;
+ C := (Inst => Make_Instance (Syn_Inst, Info, C_Sname),
T_En => True,
W_En => No_Wire_Id,
W_Ret => No_Wire_Id,
@@ -1436,15 +1443,12 @@ package body Synth.Stmts is
Ret_Value => null,
Ret_Typ => null,
Nbr_Ret => 0);
+
+
Mark (M, Proc_Pool);
Instance_Pool := Proc_Pool'Access;
if Is_Valid (Decls_Chain) then
- if Label = Null_Identifier then
- C.Inst.Name := New_Internal_Name (Build_Context, Syn_Inst.Name);
- else
- C.Inst.Name := New_Sname (Syn_Inst.Name, Label);
- end if;
Synth_Declarations (C.Inst, Decls_Chain);
end if;
@@ -1493,7 +1497,8 @@ package body Synth.Stmts is
end;
Areapools.Mark (M, Instance_Pool.all);
- C := (Inst => Make_Instance (Syn_Inst, Get_Info (Bod)),
+ C := (Inst => Make_Instance (Syn_Inst, Get_Info (Bod),
+ New_Internal_Name (Build_Context)),
T_En => True,
W_En => No_Wire_Id,
W_Ret => Alloc_Wire (Wire_Variable, Imp),
@@ -1502,7 +1507,6 @@ package body Synth.Stmts is
Ret_Value => null,
Ret_Typ => null,
Nbr_Ret => 0);
- C.Inst.Name := New_Internal_Name (Build_Context);
Synth_Subprogram_Association
(C.Inst, Syn_Inst, Inter_Chain, Assoc_Chain);
@@ -1823,16 +1827,16 @@ package body Synth.Stmts is
Decls_Chain : constant Node := Get_Declaration_Chain (Bod);
Prev_Instance_Pool : constant Areapool_Acc := Instance_Pool;
Bod_Inst : Synth_Instance_Acc;
+ Bod_Sname : Sname;
M : Areapools.Mark_Type;
begin
- Bod_Inst := Make_Instance (Syn_Inst, Info);
+ Bod_Sname := New_Sname (Get_Sname (Syn_Inst), Get_Identifier (Bod));
+ Bod_Inst := Make_Instance (Syn_Inst, Info, Bod_Sname);
-- Same module.
- Bod_Inst.M := Syn_Inst.M;
+ Set_Module (Bod_Inst, Get_Module (Syn_Inst));
Mark (M, Proc_Pool);
Instance_Pool := Proc_Pool'Access;
- Bod_Inst.Name := New_Sname (Syn_Inst.Name, Get_Identifier (Bod));
-
if Iterator /= Null_Node then
-- Add the iterator (for for-generate).
Create_Object (Bod_Inst, Iterator, Iterator_Val);
diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb
index a854c34cc..13371b122 100644
--- a/src/synth/synthesis.adb
+++ b/src/synth/synthesis.adb
@@ -63,7 +63,7 @@ package body Synthesis is
if Parent_Inst /= Global_Instance then
Create_Object (Parent_Inst, Pkg, Val);
else
- Parent_Inst.Objects (Info.Pkg_Slot) := Val;
+ Create_Package_Object (Parent_Inst, Pkg, Val);
end if;
Synth_Declarations (Syn_Inst, Get_Declaration_Chain (Pkg));
if Pkg = Vhdl.Std_Package.Standard_Package then