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author | Tristan Gingold <tgingold@free.fr> | 2023-04-18 21:14:17 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-04-18 21:14:50 +0200 |
commit | aaeeda7eb30b827c7fb690550d85ab6a915ef7f8 (patch) | |
tree | eb3db7a33c52b89fa3a9eec7d88a1e281bfdb44b /src/synth | |
parent | 04b44b782355c0661b6ec7053f204da9b6185759 (diff) | |
download | ghdl-aaeeda7eb30b827c7fb690550d85ab6a915ef7f8.tar.gz ghdl-aaeeda7eb30b827c7fb690550d85ab6a915ef7f8.tar.bz2 ghdl-aaeeda7eb30b827c7fb690550d85ab6a915ef7f8.zip |
synth: add create_value_net with a pool parameter
Diffstat (limited to 'src/synth')
-rw-r--r-- | src/synth/elab-vhdl_values.adb | 7 | ||||
-rw-r--r-- | src/synth/elab-vhdl_values.ads | 3 | ||||
-rw-r--r-- | src/synth/synth-vhdl_context.adb | 10 | ||||
-rw-r--r-- | src/synth/synth-vhdl_context.ads | 1 | ||||
-rw-r--r-- | src/synth/synth-vhdl_decls.adb | 12 |
5 files changed, 17 insertions, 16 deletions
diff --git a/src/synth/elab-vhdl_values.adb b/src/synth/elab-vhdl_values.adb index 0a1a4b982..724e961b5 100644 --- a/src/synth/elab-vhdl_values.adb +++ b/src/synth/elab-vhdl_values.adb @@ -105,13 +105,14 @@ package body Elab.Vhdl_Values is return To_Value_Acc (Alloc (Pool, (Kind => Value_Wire, N => S))); end Create_Value_Wire; - function Create_Value_Net (S : Uns32) return Value_Acc + function Create_Value_Net (S : Uns32; Pool : Areapool_Acc) + return Value_Acc is subtype Value_Type_Net is Value_Type (Value_Net); function Alloc is new Areapools.Alloc_On_Pool_Addr (Value_Type_Net); begin return To_Value_Acc - (Alloc (Current_Pool, Value_Type_Net'(Kind => Value_Net, N => S))); + (Alloc (Pool, Value_Type_Net'(Kind => Value_Net, N => S))); end Create_Value_Net; function Create_Value_Signal (S : Signal_Index_Type; Init : Value_Acc) @@ -306,7 +307,7 @@ package body Elab.Vhdl_Values is Res := Create_Value_Memory (Src.Typ, Current_Pool); Copy_Memory (Res.Val.Mem, Src.Val.Mem, Src.Typ.Sz); when Value_Net => - Res := (Src.Typ, Create_Value_Net (Src.Val.N)); + Res := (Src.Typ, Create_Value_Net (Src.Val.N, Current_Pool)); when Value_Wire => Res := (Src.Typ, Create_Value_Wire (Src.Val.N, Current_Pool)); when Value_File => diff --git a/src/synth/elab-vhdl_values.ads b/src/synth/elab-vhdl_values.ads index 21ea4a35b..c4482c71c 100644 --- a/src/synth/elab-vhdl_values.ads +++ b/src/synth/elab-vhdl_values.ads @@ -140,7 +140,8 @@ package Elab.Vhdl_Values is function Is_Equal (L, R : Valtyp) return Boolean; -- Create a Value_Net. - function Create_Value_Net (S : Uns32) return Value_Acc; + function Create_Value_Net (S : Uns32; Pool : Areapool_Acc) + return Value_Acc; -- Create a Value_Wire. function Create_Value_Wire (S : Uns32; Pool : Areapool_Acc) diff --git a/src/synth/synth-vhdl_context.adb b/src/synth/synth-vhdl_context.adb index 55f9f795d..81898157f 100644 --- a/src/synth/synth-vhdl_context.adb +++ b/src/synth/synth-vhdl_context.adb @@ -384,18 +384,16 @@ package body Synth.Vhdl_Context is return (Wtype, Create_Value_Wire (W, Pool)); end Create_Value_Wire; - function Create_Value_Net (N : Net) return Value_Acc + function Create_Value_Net (N : Net; Pool : Areapool_Acc) return Value_Acc is function To_Uns32 is new Ada.Unchecked_Conversion (Net, Uns32); begin - return Create_Value_Net (To_Uns32 (N)); + return Create_Value_Net (To_Uns32 (N), Pool); end Create_Value_Net; - function Create_Value_Net (N : Net; Ntype : Type_Acc) return Valtyp - is - pragma Assert (Ntype /= null); + function Create_Value_Net (N : Net; Ntype : Type_Acc) return Valtyp is begin - return (Ntype, Create_Value_Net (N)); + return (Ntype, Create_Value_Net (N, Current_Pool)); end Create_Value_Net; function Create_Value_Dyn_Alias (Obj : Value_Acc; diff --git a/src/synth/synth-vhdl_context.ads b/src/synth/synth-vhdl_context.ads index 396f0718d..94dc401d4 100644 --- a/src/synth/synth-vhdl_context.ads +++ b/src/synth/synth-vhdl_context.ads @@ -104,6 +104,7 @@ package Synth.Vhdl_Context is pragma Inline (Set_Value_Wire); -- Create a Value_Net. + function Create_Value_Net (N : Net; Pool : Areapool_Acc) return Value_Acc; function Create_Value_Net (N : Net; Ntype : Type_Acc) return Valtyp; -- Create a Value_Wire. For a bit wire, RNG must be null. diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb index 19473775f..90c5de474 100644 --- a/src/synth/synth-vhdl_decls.adb +++ b/src/synth/synth-vhdl_decls.adb @@ -659,12 +659,12 @@ package body Synth.Vhdl_Decls is if Aval.Val.Kind = Value_Net then -- Object is a net if it is not writable. Extract the -- bits for the alias. - Current_Pool := Instance_Pool; - Aval := Create_Value_Net - (Build2_Extract (Get_Build (Syn_Inst), Get_Value_Net (Aval.Val), - Off, Val.Typ.W), - Val.Typ); - Current_Pool := Expr_Pool'Access; + Aval := (Val.Typ, + Create_Value_Net (Build2_Extract + (Get_Build (Syn_Inst), + Get_Value_Net (Aval.Val), + Off, Val.Typ.W), + Instance_Pool)); Val.Val.A_Off := (0, 0); else Aval := Unshare (Aval, Instance_Pool); |