synth: simplify id_dyn_extract.

5 files changed, 9 insertions, 22 deletions

diff --git a/src/synth/netlists-builders.adb b/src/synth/netlists-builders.adb
index f27d82723..86d940379 100644
--- a/src/synth/netlists-builders.adb
+++ b/src/synth/netlists-builders.adb
@@ -215,16 +215,14 @@ package body Netlists.Builders is
    begin
       Res := New_User_Module
         (Ctxt.Design, New_Sname_Artificial (Get_Identifier ("dyn_extract")),
-         Id_Dyn_Extract, 2, 1, 2);
+         Id_Dyn_Extract, 2, 1, 1);
       Ctxt.M_Dyn_Extract := Res;
       Outputs := (0 => Create_Output ("o"));
       Inputs := (0 => Create_Input ("i"),
                  1 => Create_Input ("v"));
       Set_Port_Desc (Res, Inputs, Outputs);
       Set_Param_Desc
-        (Res, (0 => (New_Sname_Artificial (Get_Identifier ("step")),
-                     Typ => Param_Uns32),
-               1 => (New_Sname_Artificial (Get_Identifier ("offset")),
+        (Res, (0 => (New_Sname_Artificial (Get_Identifier ("offset")),
                      Typ => Param_Uns32)));
    end Create_Dyn_Extract_Module;
 
@@ -1191,8 +1189,7 @@ package body Netlists.Builders is
    end Build2_Extract;
 
    function Build_Dyn_Extract
-     (Ctxt : Context_Acc;
-      I : Net; P : Net; Step : Uns32; Off : Uns32; W : Width) return Net
+     (Ctxt : Context_Acc; I : Net; P : Net; Off : Uns32; W : Width) return Net
    is
       Wd : constant Width := Get_Width (I);
       pragma Assert (Wd /= No_Width);
@@ -1205,8 +1202,7 @@ package body Netlists.Builders is
       Set_Width (O, W);
       Connect (Get_Input (Inst, 0), I);
       Connect (Get_Input (Inst, 1), P);
-      Set_Param_Uns32 (Inst, 0, Step);
-      Set_Param_Uns32 (Inst, 1, Off);
+      Set_Param_Uns32 (Inst, 0, Off);
       return O;
    end Build_Dyn_Extract;
 
diff --git a/src/synth/netlists-builders.ads b/src/synth/netlists-builders.ads
index 920395cf8..581e70602 100644
--- a/src/synth/netlists-builders.ads
+++ b/src/synth/netlists-builders.ads
@@ -129,8 +129,7 @@ package Netlists.Builders is
    function Build_Extract_Bit
      (Ctxt : Context_Acc; I : Net; Off : Width) return Net;
    function Build_Dyn_Extract
-     (Ctxt : Context_Acc;
-      I : Net; P : Net; Step : Uns32; Off : Uns32; W : Width) return Net;
+     (Ctxt : Context_Acc; I : Net; P : Net; Off : Uns32; W : Width) return Net;
 
    function Build_Dyn_Insert
      (Ctxt : Context_Acc; I : Net; V : Net; P : Net; Step : Uns32; Off : Uns32)
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb
index fed799508..b0fd454a1 100644
--- a/src/synth/netlists-disp_vhdl.adb
+++ b/src/synth/netlists-disp_vhdl.adb
@@ -605,22 +605,15 @@ package body Netlists.Disp_Vhdl is
             declare
                O : constant Net := Get_Output (Inst, 0);
                Wd : constant Width := Get_Width (O);
-               Step : constant Uns32 := Get_Param_Uns32 (Inst, 0);
-               Off : constant Uns32 := Get_Param_Uns32 (Inst, 1);
+               Off : constant Uns32 := Get_Param_Uns32 (Inst, 0);
             begin
                Disp_Template ("  \o0 <= \i0 (to_integer (\ui1)", Inst);
-               if Step /= 1 then
-                  Disp_Template (" * \n0", Inst, (0 => Step));
-               end if;
                if Off /= 0 then
                   Disp_Template (" + \n0", Inst, (0 => Off));
                end if;
                if Wd > 1 then
                   Disp_Template (" + \n0 - 1 downto to_integer (\ui1)",
                                  Inst, (0 => Wd));
-                  if Step /= 1 then
-                     Disp_Template (" * \n0", Inst, (0 => Step));
-                  end if;
                   if Off /= 0 then
                      Disp_Template (" + \n0", Inst, (0 => Off));
                   end if;
diff --git a/src/synth/netlists-gates.ads b/src/synth/netlists-gates.ads
index 818a7eee2..4ba14e137 100644
--- a/src/synth/netlists-gates.ads
+++ b/src/synth/netlists-gates.ads
@@ -144,7 +144,7 @@ package Netlists.Gates is
    --  OUT := IN0[OFF+WD-1:OFF]
    Id_Extract : constant Module_Id := 68;
 
-   --  OUT := IN0[IN1*STEP+OFF+WD-1:IN1*STEP+OFF]
+   --  OUT := IN0[IN1+OFF+WD-1:IN1+OFF]
    Id_Dyn_Extract : constant Module_Id := 69;
 
    --  Like Insert but for dynamic values.
diff --git a/src/synth/synth-expr.adb b/src/synth/synth-expr.adb
index 03a91155e..f0ba02b40 100644
--- a/src/synth/synth-expr.adb
+++ b/src/synth/synth-expr.adb
@@ -1002,7 +1002,7 @@ package body Synth.Expr is
       else
          pragma Assert (Off = 0);
          Res := Build_Dyn_Extract (Build_Context, Get_Net (Pfx_Val),
-                                   Voff, 1, Off, W);
+                                   Voff, Off, W);
          Set_Location (Res, Name);
          return Create_Value_Net (Res, El_Typ);
       end if;
@@ -1293,8 +1293,7 @@ package body Synth.Expr is
       Synth_Slice_Suffix (Syn_Inst, Name, Pfx_Bnd, El_Typ.W,
                           Res_Bnd, Inp, Off, Wd);
       if Inp /= No_Net then
-         N := Build_Dyn_Extract (Build_Context,
-                                 Get_Net (Pfx), Inp, 1, Off, Wd);
+         N := Build_Dyn_Extract (Build_Context, Get_Net (Pfx), Inp, Off, Wd);
          Set_Location (N, Name);
          --  TODO: the bounds cannot be created as they are not known.
          Res_Type := Create_Slice_Type (Wd, El_Typ);