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| author | Tristan Gingold <tgingold@free.fr> | 2020-02-18 20:26:50 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-02-18 20:27:12 +0100 |
| commit | 493fe4337300dbcfd796715bd7268347ba849950 (patch) | |
| tree | 9bb516d249d51eb4e1f1cfa6cb531898a4ccc82c /src/synth | |
| parent | 26aefc178f1f2d1eee9f0e48d919adb56b274466 (diff) | |
| download | ghdl-493fe4337300dbcfd796715bd7268347ba849950.tar.gz ghdl-493fe4337300dbcfd796715bd7268347ba849950.tar.bz2 ghdl-493fe4337300dbcfd796715bd7268347ba849950.zip | |
vhdl: recognize conversion functions from std_logic_1164
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/synth-oper.adb | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/synth/synth-oper.adb b/src/synth/synth-oper.adb index ec32aa1f0..a185eef17 100644 --- a/src/synth/synth-oper.adb +++ b/src/synth/synth-oper.adb @@ -1270,7 +1270,8 @@ package body Synth.Oper is end if; return Create_Value_Net (Get_Net (L), Create_Res_Bound (L)); end; - when Iir_Predefined_Ieee_1164_To_Stdlogicvector => + when Iir_Predefined_Ieee_1164_To_Stdlogicvector_Suv + | Iir_Predefined_Ieee_1164_To_Stdlogicvector_Bv => declare L : constant Value_Acc := Get_Value (Subprg_Inst, Param1); begin |