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| author | Tristan Gingold <tgingold@free.fr> | 2019-12-05 22:30:51 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-12-05 22:30:51 +0100 |
| commit | 0b4b7c215f02da9c741a570b1e0c7bf9de35345b (patch) | |
| tree | 2d2a3820754f7f632493351b0a353a430eca0d9e /src/synth | |
| parent | a2f3facf69731165a3f5469de350be4c12e933a6 (diff) | |
| download | ghdl-0b4b7c215f02da9c741a570b1e0c7bf9de35345b.tar.gz ghdl-0b4b7c215f02da9c741a570b1e0c7bf9de35345b.tar.bz2 ghdl-0b4b7c215f02da9c741a570b1e0c7bf9de35345b.zip | |
netlists-disp_vhdl: handle id_mem_rd_sync
Diffstat (limited to 'src/synth')
| -rw-r--r-- | src/synth/netlists-disp_vhdl.adb | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/src/synth/netlists-disp_vhdl.adb b/src/synth/netlists-disp_vhdl.adb index 4095ece78..e053716d9 100644 --- a/src/synth/netlists-disp_vhdl.adb +++ b/src/synth/netlists-disp_vhdl.adb @@ -622,11 +622,17 @@ package body Netlists.Disp_Vhdl is Port_Inst := Get_Input_Parent (Get_First_Sink (Port)); case Get_Id (Port_Inst) is when Id_Mem_Wr_Sync => + -- Clock S := Get_Input_Net (Port_Inst, 2); Data_W := Get_Width (Get_Input_Net (Port_Inst, 4)); when Id_Mem_Rd => + -- Address S := Get_Input_Net (Port_Inst, 1); Data_W := Get_Width (Get_Output (Port_Inst, 1)); + when Id_Mem_Rd_Sync => + -- Clock + S := Get_Input_Net (Port_Inst, 2); + Data_W := Get_Width (Get_Output (Port_Inst, 1)); when others => raise Internal_Error; end case; @@ -671,6 +677,14 @@ package body Netlists.Disp_Vhdl is Disp_Template (" \o1 <= ", Port_Inst); Disp_Template ("\o0", Mem); Disp_Template ("(to_integer (\ui1));" & NL, Port_Inst); + when Id_Mem_Rd_Sync => + Disp_Template + (" if rising_edge(\i2) and (\fi3 = '1') then" & NL, + Port_Inst); + Disp_Template (" \o1 <= ", Port_Inst); + Disp_Template ("\o0", Mem); + Disp_Template ("(to_integer (\ui1));" & NL, Port_Inst); + Put_Line (" end if;"); when others => raise Internal_Error; end case; @@ -707,6 +721,7 @@ package body Netlists.Disp_Vhdl is | Id_Memory_Init => Disp_Memory (Inst); when Id_Mem_Rd + | Id_Mem_Rd_Sync | Id_Mem_Wr_Sync => null; when Id_Output => |