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authorTristan Gingold <tgingold@free.fr>2021-11-09 20:54:19 +0100
committerTristan Gingold <tgingold@free.fr>2021-11-09 20:54:19 +0100
commit96245c0a4df7a6bc07cd8b7c15268c78c459f3b7 (patch)
tree8c9aacd46303689492872db13bb71cb2a61ba44a /src/synth/synthesis.adb
parent144cedec159574df474579fa2cc7fde7e61eadbc (diff)
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vhdl: Iir_Kind_Foreign_Module is now a library unit
(instead of a design unit). Also, add Iir_Kind_Foreign_Vector_Type_Definition
Diffstat (limited to 'src/synth/synthesis.adb')
-rw-r--r--src/synth/synthesis.adb19
1 files changed, 10 insertions, 9 deletions
diff --git a/src/synth/synthesis.adb b/src/synth/synthesis.adb
index 57d20df13..8a2f3de67 100644
--- a/src/synth/synthesis.adb
+++ b/src/synth/synthesis.adb
@@ -50,18 +50,19 @@ package body Synthesis is
Encoding : Name_Encoding) return Module
is
Base : Base_Instance_Acc;
+ Unit : Iir;
begin
Base := Make_Base_Instance;
- case Iir_Kinds_Design_Unit (Get_Kind (Design)) is
- when Iir_Kind_Foreign_Module =>
- if Synth_Top_Foreign = null then
- raise Internal_Error;
- end if;
- Synth_Top_Foreign (Base, Get_Foreign_Node (Design), Encoding);
- when Iir_Kind_Design_Unit =>
- Synth_Top_Entity (Base, Design, Encoding, Inst);
- end case;
+ Unit := Get_Library_Unit (Design);
+ if Get_Kind (Unit) = Iir_Kind_Foreign_Module then
+ if Synth_Top_Foreign = null then
+ raise Internal_Error;
+ end if;
+ Synth_Top_Foreign (Base, Get_Foreign_Node (Unit), Encoding);
+ else
+ Synth_Top_Entity (Base, Design, Encoding, Inst);
+ end if;
Synth.Vhdl_Insts.Synth_All_Instances;