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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-03 16:36:48 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-03 16:36:48 +0200 |
| commit | 926dff10e4ed121e08c18c2f77030e5962308966 (patch) | |
| tree | ebdf39140fa53e68f34a9fa275d7b748632c8336 /src/synth/synth-vhdl_stmts.adb | |
| parent | c7ac60b0835b1017b62ae106f0d48eef9efc65df (diff) | |
| download | ghdl-926dff10e4ed121e08c18c2f77030e5962308966.tar.gz ghdl-926dff10e4ed121e08c18c2f77030e5962308966.tar.bz2 ghdl-926dff10e4ed121e08c18c2f77030e5962308966.zip | |
synth: avoid crash on invalid hdl in psl. Fix #2204
Diffstat (limited to 'src/synth/synth-vhdl_stmts.adb')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 40a694940..b122c11ff 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -4217,6 +4217,7 @@ package body Synth.Vhdl_Stmts is Cond : Net; E : NFA_Edge; D_Arr : Net_Array_Acc; + N : Net; Res : Net; begin D_Arr := new Net_Array'(0 .. Nbr_States - 1 => No_Net); @@ -4232,10 +4233,14 @@ package body Synth.Vhdl_Stmts is E := Get_First_Src_Edge (S); while E /= No_Edge loop -- Edge condition. - Cond := Build_Dyadic - (Ctxt, Id_And, - I, Synth_PSL_Expression (Syn_Inst, Get_Edge_Expr (E))); - Set_Location (Cond, Loc); + N := Synth_PSL_Expression (Syn_Inst, Get_Edge_Expr (E)); + if N = No_Net then + -- Anything ? + Cond := I; + else + Cond := Build_Dyadic (Ctxt, Id_And, I, N); + Set_Location (Cond, Loc); + end if; -- TODO: if EOS is present, then this is a live state. |