diff options
| author | Tristan Gingold <tgingold@free.fr> | 2022-09-28 06:43:44 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-28 06:43:44 +0200 |
| commit | 5993986a91f3f41813b890e6b9d10cc5a3beea17 (patch) | |
| tree | abc04887c28d2784983f80d7ed161a7d1a19ea5b /src/synth/synth-vhdl_stmts.adb | |
| parent | e15f01013928d7023a1f6d4bc93aa59fef9bffcf (diff) | |
| download | ghdl-5993986a91f3f41813b890e6b9d10cc5a3beea17.tar.gz ghdl-5993986a91f3f41813b890e6b9d10cc5a3beea17.tar.bz2 ghdl-5993986a91f3f41813b890e6b9d10cc5a3beea17.zip | |
synth: handle null-range loops
Diffstat (limited to 'src/synth/synth-vhdl_stmts.adb')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 37 |
1 files changed, 23 insertions, 14 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index d6ee49bab..bf30d8e08 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -3277,6 +3277,7 @@ package body Synth.Vhdl_Stmts is is Stmts : constant Node := Get_Sequential_Statement_Chain (Stmt); Val : Valtyp; + Valid : Boolean; Lc : aliased Loop_Context (Mode_Dynamic); begin Lc := (Mode => Mode_Dynamic, @@ -3293,17 +3294,21 @@ package body Synth.Vhdl_Stmts is Init_For_Loop_Statement (C.Inst, Stmt, Val); - while In_Range (Val.Typ.Drange, Read_Discrete (Val)) loop - Synth_Sequential_Statements (C, Stmts); + if In_Range (Val.Typ.Drange, Read_Discrete (Val)) then + loop + Synth_Sequential_Statements (C, Stmts); - Update_Index (Val.Typ.Drange, Val); - Loop_Control_Update (C); + Loop_Control_Update (C); - -- Constant exit. - exit when Is_Static_Bit0 (C.W_En); + -- Constant exit. + exit when Is_Static_Bit0 (C.W_En); - -- FIXME: dynamic exits. - end loop; + Update_Index (Val.Typ.Drange, Valid, Val); + exit when not Valid; + + -- FIXME: dynamic exits. + end loop; + end if; Loop_Control_Finish (C); Finish_For_Loop_Statement (C.Inst, Stmt); @@ -3316,6 +3321,7 @@ package body Synth.Vhdl_Stmts is is Stmts : constant Node := Get_Sequential_Statement_Chain (Stmt); Val : Valtyp; + Valid : Boolean; Lc : aliased Loop_Context (Mode_Static); begin Lc := (Mode_Static, @@ -3327,14 +3333,17 @@ package body Synth.Vhdl_Stmts is Init_For_Loop_Statement (C.Inst, Stmt, Val); - while In_Range (Val.Typ.Drange, Read_Discrete (Val)) loop - Synth_Sequential_Statements (C, Stmts); - C.S_En := True; + if In_Range (Val.Typ.Drange, Read_Discrete (Val)) then + loop + Synth_Sequential_Statements (C, Stmts); + C.S_En := True; - Update_Index (Val.Typ.Drange, Val); + Update_Index (Val.Typ.Drange, Valid, Val); + exit when not Valid; - exit when Lc.S_Exit or Lc.S_Quit or C.Nbr_Ret > 0; - end loop; + exit when Lc.S_Exit or Lc.S_Quit or C.Nbr_Ret > 0; + end loop; + end if; Finish_For_Loop_Statement (C.Inst, Stmt); |