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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-14 09:42:37 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-14 19:36:41 +0100 |
| commit | 3fd2769300e7ff6e2065dbbbf4cbb44fa11fbda0 (patch) | |
| tree | ba4966774c5e1c019c10be062b68ad9c36a97e43 /src/synth/synth-vhdl_stmts.adb | |
| parent | 7052ac9006b145c0cd51f2bad8e088c1338f3846 (diff) | |
| download | ghdl-3fd2769300e7ff6e2065dbbbf4cbb44fa11fbda0.tar.gz ghdl-3fd2769300e7ff6e2065dbbbf4cbb44fa11fbda0.tar.bz2 ghdl-3fd2769300e7ff6e2065dbbbf4cbb44fa11fbda0.zip | |
synth: more refactoring
Diffstat (limited to 'src/synth/synth-vhdl_stmts.adb')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 24 |
1 files changed, 11 insertions, 13 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 977741469..a0870cdd1 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -222,7 +222,6 @@ package body Synth.Vhdl_Stmts is end Synth_Assignment_Prefix_Slice_Name; procedure Synth_Assignment_Prefix (Syn_Inst : Synth_Instance_Acc; - Inter_Inst : Synth_Instance_Acc; Pfx : Node; Dest_Base : out Valtyp; Dest_Typ : out Type_Acc; @@ -251,13 +250,13 @@ package body Synth.Vhdl_Stmts is | Iir_Kind_Selected_Name | Iir_Kind_Attribute_Name => Synth_Assignment_Prefix - (Syn_Inst, Inter_Inst, Get_Named_Entity (Pfx), + (Syn_Inst, Get_Named_Entity (Pfx), Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn); when Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_File_Declaration => - Assign_Base (Inter_Inst); + Assign_Base (Syn_Inst); when Iir_Kind_Variable_Declaration | Iir_Kind_Signal_Declaration | Iir_Kind_Guard_Signal_Declaration @@ -274,21 +273,21 @@ package body Synth.Vhdl_Stmts is when Iir_Kind_Indexed_Name => Synth_Assignment_Prefix - (Syn_Inst, Inter_Inst, Get_Prefix (Pfx), + (Syn_Inst, Get_Prefix (Pfx), Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn); Synth_Assignment_Prefix_Indexed_Name (Syn_Inst, Pfx, Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn); when Iir_Kind_Selected_Element => Synth_Assignment_Prefix - (Syn_Inst, Inter_Inst, Get_Prefix (Pfx), + (Syn_Inst, Get_Prefix (Pfx), Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn); Synth_Assignment_Prefix_Selected_Name (Syn_Inst, Pfx, Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn); when Iir_Kind_Slice_Name => Synth_Assignment_Prefix - (Syn_Inst, Inter_Inst, Get_Prefix (Pfx), + (Syn_Inst, Get_Prefix (Pfx), Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn); Synth_Assignment_Prefix_Slice_Name (Syn_Inst, Pfx, Dest_Base, Dest_Typ, Dest_Off, Dest_Dyn); @@ -338,7 +337,7 @@ package body Synth.Vhdl_Stmts is Dyn : Dyn_Name; begin Synth_Assignment_Prefix - (Syn_Inst, Syn_Inst, Pfx, Dest_Base, Dest_Typ, Dest_Off, Dyn); + (Syn_Inst, Pfx, Dest_Base, Dest_Typ, Dest_Off, Dyn); pragma Assert (Dyn = No_Dyn_Name); end Synth_Assignment_Prefix; @@ -471,7 +470,7 @@ package body Synth.Vhdl_Stmts is Dyn : Dyn_Name; begin Synth_Assignment_Prefix - (Syn_Inst, Syn_Inst, Target, Base, Typ, Off, Dyn); + (Syn_Inst, Target, Base, Typ, Off, Dyn); return To_Target_Info (Base, Typ, Off, Dyn); end; when others => @@ -2129,7 +2128,7 @@ package body Synth.Vhdl_Stmts is end Copy_Unbounded_Type; procedure Synth_Individual_Formal (Syn_Inst : Synth_Instance_Acc; - Formal : Valtyp; + Formal : Type_Acc; Pfx : Node; Dest_Typ : out Type_Acc; Dest_Off : out Value_Offsets) is @@ -2143,7 +2142,7 @@ package body Synth.Vhdl_Stmts is | Iir_Kind_Interface_Variable_Declaration | Iir_Kind_Interface_Constant_Declaration | Iir_Kind_Interface_File_Declaration => - Dest_Typ := Formal.Typ; + Dest_Typ := Formal; Dest_Off := No_Value_Offsets; when Iir_Kind_Indexed_Name => @@ -2238,7 +2237,7 @@ package body Synth.Vhdl_Stmts is Cb_Val : Valtyp; begin Synth_Individual_Formal - (Caller_Inst, Res, Formal, Form_Typ, Form_Off); + (Caller_Inst, Formal_Typ, Formal, Form_Typ, Form_Off); if Inter_Kind = Iir_Kind_Interface_Constant_Declaration then Act_Base := Synth_Expression_With_Type @@ -2248,8 +2247,7 @@ package body Synth.Vhdl_Stmts is Act_Dyn := No_Dyn_Name; else Synth_Assignment_Prefix - (Caller_Inst, Caller_Inst, - Actual, Act_Base, Act_Typ, Act_Off, Act_Dyn); + (Caller_Inst, Actual, Act_Base, Act_Typ, Act_Off, Act_Dyn); end if; if Get_Actual_Conversion (Assoc) /= Null_Node then -- TODO |