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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-13 03:05:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-13 03:07:47 +0200 |
| commit | 256bda5593e44bc2d95ebaf855ff00d4042f2a03 (patch) | |
| tree | f3cc12abd7673f7e33f639dd816778818f864321 /src/synth/synth-vhdl_stmts.adb | |
| parent | 7fc415a0cd6f6504e0fefb6f960dd4cbc7fbf047 (diff) | |
| download | ghdl-256bda5593e44bc2d95ebaf855ff00d4042f2a03.tar.gz ghdl-256bda5593e44bc2d95ebaf855ff00d4042f2a03.tar.bz2 ghdl-256bda5593e44bc2d95ebaf855ff00d4042f2a03.zip | |
synth-vhdl_stmts(synth_verification_unit): always set instance_pool.
Fix #2214
Diffstat (limited to 'src/synth/synth-vhdl_stmts.adb')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index b64b6ec5a..ed2aeccb8 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -4770,10 +4770,12 @@ package body Synth.Vhdl_Stmts is Get_Sname (Syn_Inst)); Set_Extra (Syn_Inst, Parent_Inst, Unit_Sname); Mark (M, Proc_Pool); - Instance_Pool := Proc_Pool'Access; Item := Get_Vunit_Item_Chain (Unit); while Item /= Null_Node loop + -- Always set instance_pool. + -- (it is cleared by synth_concurrent_statement). + Instance_Pool := Proc_Pool'Access; case Get_Kind (Item) is when Iir_Kind_Psl_Default_Clock | Iir_Kind_Psl_Declaration |