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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-26 07:53:37 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-26 07:53:37 +0200 |
| commit | 0253646671c6000da87d12bebb2166284273ae04 (patch) | |
| tree | 45bfefa0b44858efa7378d8567650d97e3ea8153 /src/synth/synth-vhdl_stmts.adb | |
| parent | 476236deae896de421daab68890e2e2473caf13d (diff) | |
| download | ghdl-0253646671c6000da87d12bebb2166284273ae04.tar.gz ghdl-0253646671c6000da87d12bebb2166284273ae04.tar.bz2 ghdl-0253646671c6000da87d12bebb2166284273ae04.zip | |
synth: handle attributes in configurations
Diffstat (limited to 'src/synth/synth-vhdl_stmts.adb')
| -rw-r--r-- | src/synth/synth-vhdl_stmts.adb | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_stmts.adb b/src/synth/synth-vhdl_stmts.adb index 141ea05ff..df8f9994d 100644 --- a/src/synth/synth-vhdl_stmts.adb +++ b/src/synth/synth-vhdl_stmts.adb @@ -393,6 +393,7 @@ package body Synth.Vhdl_Stmts is (Syn_Inst, Target), Aggr => Target); when Iir_Kind_Simple_Name + | Iir_Kind_Selected_Name | Iir_Kind_Selected_Element | Iir_Kind_Interface_Signal_Declaration | Iir_Kind_Signal_Declaration |