synth: do full elaboration before synthesis

1 files changed, 5 insertions, 4 deletions

diff --git a/src/synth/synth-vhdl_static_proc.adb b/src/synth/synth-vhdl_static_proc.adb
index 462896451..5dc31318b 100644
--- a/src/synth/synth-vhdl_static_proc.adb
+++ b/src/synth/synth-vhdl_static_proc.adb
@@ -18,10 +18,11 @@
 
 with Vhdl.Errors; use Vhdl.Errors;
 
-with Synth.Values; use Synth.Values;
+with Elab.Vhdl_Values; use Elab.Vhdl_Values;
+with Elab.Vhdl_Heap;
+with Elab.Vhdl_Files; use Elab.Vhdl_Files;
+
 with Synth.Errors; use Synth.Errors;
-with Synth.Vhdl_Files; use Synth.Vhdl_Files;
-with Synth.Vhdl_Heap;
 
 package body Synth.Vhdl_Static_Proc is
 
@@ -33,7 +34,7 @@ package body Synth.Vhdl_Static_Proc is
    begin
       Val := Read_Access (Param);
       if Val /= Null_Heap_Index then
-         Synth.Vhdl_Heap.Synth_Deallocate (Val);
+         Elab.Vhdl_Heap.Synth_Deallocate (Val);
          Write_Access (Param.Val.Mem, Null_Heap_Index);
       end if;
    end Synth_Deallocate;