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author | Tristan Gingold <tgingold@free.fr> | 2023-01-30 18:59:31 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-01-30 19:17:28 +0100 |
commit | 4863badab145faf21f31a76997c7bb7274320502 (patch) | |
tree | 12e4d33e4346a534d4bc58edcd2c90c7b082d355 /src/synth/synth-vhdl_expr.ads | |
parent | 75fa271425d1be151bb451c1b14539cc4dc428ed (diff) | |
download | ghdl-4863badab145faf21f31a76997c7bb7274320502.tar.gz ghdl-4863badab145faf21f31a76997c7bb7274320502.tar.bz2 ghdl-4863badab145faf21f31a76997c7bb7274320502.zip |
simul: use same packing order for nets and for values.
Diffstat (limited to 'src/synth/synth-vhdl_expr.ads')
-rw-r--r-- | src/synth/synth-vhdl_expr.ads | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_expr.ads b/src/synth/synth-vhdl_expr.ads index cdffd0f68..6bd109c73 100644 --- a/src/synth/synth-vhdl_expr.ads +++ b/src/synth/synth-vhdl_expr.ads @@ -119,6 +119,7 @@ package Synth.Vhdl_Expr is procedure Synth_Slice_Suffix (Syn_Inst : Synth_Instance_Acc; Name : Node; Pfx_Bnd : Bound_Type; + Order : Wkind_Type; El_Typ : Type_Acc; Res_Bnd : out Bound_Type; Inp : out Net; |