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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-06 20:38:08 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-06 20:38:08 +0200 |
| commit | a0540030ea458ed15847de7641aaa4175bb631ac (patch) | |
| tree | e395fe94c4e21c2ac7814d4de0d362d13d054783 /src/synth/synth-vhdl_decls.adb | |
| parent | e985ae703948268ba9ee3127a7d8e5b5c188ce6e (diff) | |
| download | ghdl-a0540030ea458ed15847de7641aaa4175bb631ac.tar.gz ghdl-a0540030ea458ed15847de7641aaa4175bb631ac.tar.bz2 ghdl-a0540030ea458ed15847de7641aaa4175bb631ac.zip | |
simul: complete concurrent procedure calls
Diffstat (limited to 'src/synth/synth-vhdl_decls.adb')
| -rw-r--r-- | src/synth/synth-vhdl_decls.adb | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/src/synth/synth-vhdl_decls.adb b/src/synth/synth-vhdl_decls.adb index d8c074cd4..7732e47ec 100644 --- a/src/synth/synth-vhdl_decls.adb +++ b/src/synth/synth-vhdl_decls.adb @@ -723,8 +723,6 @@ package body Synth.Vhdl_Decls is declare Val : Valtyp; begin - pragma Assert (Areapools.Is_Empty (Expr_Pool)); - Current_Pool := Instance_Pool; Val := Create_Value_Memtyp (Create_Memory_U32 (0)); Current_Pool := Expr_Pool'Access; |