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| author | Tristan Gingold <tgingold@free.fr> | 2022-05-25 05:55:12 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-05-25 06:06:55 +0200 |
| commit | 0ceba3fdfbf42443a44a2b8ad4f601fb72add5a5 (patch) | |
| tree | b6cca1e9ee8ee61018bef7206bc595742ac3b934 /src/synth/synth-vhdl_context.ads | |
| parent | 66429d454f4316155f5b94292e0e9a0c65890d01 (diff) | |
| download | ghdl-0ceba3fdfbf42443a44a2b8ad4f601fb72add5a5.tar.gz ghdl-0ceba3fdfbf42443a44a2b8ad4f601fb72add5a5.tar.bz2 ghdl-0ceba3fdfbf42443a44a2b8ad4f601fb72add5a5.zip | |
synth: add value_dyn_alias in elab-vhdl_values
Diffstat (limited to 'src/synth/synth-vhdl_context.ads')
| -rw-r--r-- | src/synth/synth-vhdl_context.ads | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/src/synth/synth-vhdl_context.ads b/src/synth/synth-vhdl_context.ads index df3e83d6a..59f18f960 100644 --- a/src/synth/synth-vhdl_context.ads +++ b/src/synth/synth-vhdl_context.ads @@ -107,6 +107,16 @@ package Synth.Vhdl_Context is -- Create a Value_Wire. For a bit wire, RNG must be null. function Create_Value_Wire (W : Wire_Id; Wtype : Type_Acc) return Valtyp; + + -- Create a Value_Dyn_Alias + function Create_Value_Dyn_Alias (Obj : Value_Acc; + Poff : Uns32; + Ptyp : Type_Acc; + Voff : Net; + Eoff : Uns32; + Typ : Type_Acc) return Valtyp; + + function Get_Value_Dyn_Alias_Voff (Val : Value_Acc) return Net; private type Extra_Vhdl_Instance_Type is record Base : Base_Instance_Acc; |