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| author | Tristan Gingold <tgingold@free.fr> | 2023-02-08 11:31:04 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-02-08 16:04:34 +0100 |
| commit | 99dbf1376808a1bffb6886811d1585e34673b078 (patch) | |
| tree | ea7b786be0ec52ac6c9501aaa813317ff60470af /src/synth/synth-vhdl_aggr.adb | |
| parent | 410f08aa700ee3c4cee834de2266ee9a09fd27bf (diff) | |
| download | ghdl-99dbf1376808a1bffb6886811d1585e34673b078.tar.gz ghdl-99dbf1376808a1bffb6886811d1585e34673b078.tar.bz2 ghdl-99dbf1376808a1bffb6886811d1585e34673b078.zip | |
synth: use same layout for records in memory as translate
Diffstat (limited to 'src/synth/synth-vhdl_aggr.adb')
| -rw-r--r-- | src/synth/synth-vhdl_aggr.adb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb index 650510e0e..1abe5a7b2 100644 --- a/src/synth/synth-vhdl_aggr.adb +++ b/src/synth/synth-vhdl_aggr.adb @@ -614,9 +614,9 @@ package body Synth.Vhdl_Aggr is (Aggr_Typ.Uarr_Idx.Drange, Iir_Index32 (Len)); case Aggr_Typ.Kind is when Type_Unbounded_Vector => - Res_Typ := Create_Vector_Type (Bnd, El_Typ); + Res_Typ := Create_Vector_Type (Bnd, False, El_Typ); when Type_Unbounded_Array => - Res_Typ := Create_Array_Type (Bnd, True, El_Typ); + Res_Typ := Create_Array_Type (Bnd, False, True, El_Typ); when others => raise Internal_Error; end case; @@ -661,7 +661,7 @@ package body Synth.Vhdl_Aggr is Els_Typ.E (I).Typ := Tab_Res (Tab_Res'Last - Nat32 (I) + 1).Typ; end loop; - Res_Typ := Create_Record_Type (Els_Typ); + Res_Typ := Create_Record_Type (Aggr_Type, Els_Typ); end; when Type_Record => Res_Typ := Aggr_Type; |