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| author | Tristan Gingold <tgingold@free.fr> | 2022-09-28 06:43:44 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-09-28 06:43:44 +0200 |
| commit | 5993986a91f3f41813b890e6b9d10cc5a3beea17 (patch) | |
| tree | abc04887c28d2784983f80d7ed161a7d1a19ea5b /src/synth/synth-vhdl_aggr.adb | |
| parent | e15f01013928d7023a1f6d4bc93aa59fef9bffcf (diff) | |
| download | ghdl-5993986a91f3f41813b890e6b9d10cc5a3beea17.tar.gz ghdl-5993986a91f3f41813b890e6b9d10cc5a3beea17.tar.bz2 ghdl-5993986a91f3f41813b890e6b9d10cc5a3beea17.zip | |
synth: handle null-range loops
Diffstat (limited to 'src/synth/synth-vhdl_aggr.adb')
| -rw-r--r-- | src/synth/synth-vhdl_aggr.adb | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb index 0df274872..192f84a70 100644 --- a/src/synth/synth-vhdl_aggr.adb +++ b/src/synth/synth-vhdl_aggr.adb @@ -284,6 +284,7 @@ package body Synth.Vhdl_Aggr is Ch : constant Node := Get_Choice_Range (Assoc); Rng : Discrete_Range_Type; Val : Valtyp; + Valid : Boolean; Rng_Len : Width; Off : Uns32; begin @@ -299,8 +300,9 @@ package body Synth.Vhdl_Aggr is Err_P := Err_P or Sub_Err; exit when Err_P; Set_Elem (First_Pos + Nat32 (Off) * Stride); - Update_Index (Rng, Val); exit when Err_P; + Update_Index (Rng, Valid, Val); + exit when not Valid; end loop; else -- The direction must be the same. |