diff options
| author | Tristan Gingold <tgingold@free.fr> | 2023-01-03 13:53:59 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-03 16:47:29 +0100 |
| commit | 45820b4ee0b61090a5f950da1485b2c635eb6396 (patch) | |
| tree | 7f987e729c4582e200658c4258290e58b4a61fcf /src/synth/synth-vhdl_aggr.adb | |
| parent | 1e5f96642bbf470934f245c98908337f75abb35a (diff) | |
| download | ghdl-45820b4ee0b61090a5f950da1485b2c635eb6396.tar.gz ghdl-45820b4ee0b61090a5f950da1485b2c635eb6396.tar.bz2 ghdl-45820b4ee0b61090a5f950da1485b2c635eb6396.zip | |
synth-vhdl_aggr: minor renaming
Diffstat (limited to 'src/synth/synth-vhdl_aggr.adb')
| -rw-r--r-- | src/synth/synth-vhdl_aggr.adb | 17 |
1 files changed, 9 insertions, 8 deletions
diff --git a/src/synth/synth-vhdl_aggr.adb b/src/synth/synth-vhdl_aggr.adb index 173850045..d0d277736 100644 --- a/src/synth/synth-vhdl_aggr.adb +++ b/src/synth/synth-vhdl_aggr.adb @@ -436,11 +436,11 @@ package body Synth.Vhdl_Aggr is function Synth_Aggregate_Array (Syn_Inst : Synth_Instance_Acc; Aggr : Node; - Aggr_Type : Type_Acc) return Valtyp + Aggr_Typ : Type_Acc) return Valtyp is Ctxt : constant Context_Acc := Get_Build (Syn_Inst); - Strides : constant Stride_Array := Fill_Stride (Aggr_Type); - Flen : constant Iir_Index32 := Get_Array_Flat_Length (Aggr_Type); + Strides : constant Stride_Array := Fill_Stride (Aggr_Typ); + Flen : constant Iir_Index32 := Get_Array_Flat_Length (Aggr_Typ); Tab_Res : Valtyp_Array_Acc; Const_P : Boolean; Err_P : Boolean; @@ -449,7 +449,7 @@ package body Synth.Vhdl_Aggr is Tab_Res := new Valtyp_Array'(1 .. Nat32 (Flen) => No_Valtyp); Fill_Array_Aggregate (Syn_Inst, Aggr, Tab_Res, - Aggr_Type, 1, Strides, 1, Const_P, Err_P); + Aggr_Typ, 1, Strides, 1, Const_P, Err_P); if Err_P then return No_Valtyp; end if; @@ -460,7 +460,7 @@ package body Synth.Vhdl_Aggr is declare Off : Size_Type; begin - Res := Create_Value_Memory (Aggr_Type, Current_Pool); + Res := Create_Value_Memory (Aggr_Typ, Current_Pool); Off := 0; for I in Tab_Res'Range loop if Tab_Res (I).Val /= null then @@ -469,11 +469,11 @@ package body Synth.Vhdl_Aggr is Off := Off + Tab_Res (I).Typ.Sz; end if; end loop; - pragma Assert (Off = Aggr_Type.Sz); + pragma Assert (Off = Aggr_Typ.Sz); end; else Res := Create_Value_Net - (Valtyp_Array_To_Net (Ctxt, Tab_Res.all), Aggr_Type); + (Valtyp_Array_To_Net (Ctxt, Tab_Res.all), Aggr_Typ); end if; Free_Valtyp_Array (Tab_Res); @@ -545,7 +545,8 @@ package body Synth.Vhdl_Aggr is Aggr_Type : Type_Acc) return Valtyp is begin case Aggr_Type.Kind is - when Type_Unbounded_Array | Type_Unbounded_Vector => + when Type_Unbounded_Array + | Type_Unbounded_Vector => declare Res_Type : Type_Acc; begin |