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author | Tristan Gingold <tgingold@free.fr> | 2019-09-08 08:00:42 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2019-09-11 06:37:27 +0200 |
commit | 1e1eab735ecad00ee663a68e3a5118e041c20739 (patch) | |
tree | 2fe36697581fd0b4e8499f3bacd2322a1cb53ae1 /src/synth/synth-values.ads | |
parent | 67333b39047b444ea93f1efcabf7ea7b0371a972 (diff) | |
download | ghdl-1e1eab735ecad00ee663a68e3a5118e041c20739.tar.gz ghdl-1e1eab735ecad00ee663a68e3a5118e041c20739.tar.bz2 ghdl-1e1eab735ecad00ee663a68e3a5118e041c20739.zip |
synth: Add width field in type_type record.
Diffstat (limited to 'src/synth/synth-values.ads')
-rw-r--r-- | src/synth/synth-values.ads | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/synth/synth-values.ads b/src/synth/synth-values.ads index a0db0f5fb..fa6f0908f 100644 --- a/src/synth/synth-values.ads +++ b/src/synth/synth-values.ads @@ -32,12 +32,14 @@ package Synth.Values is -- Netlist representation: signed or unsigned, width of vector. Is_Signed : Boolean; - W : Width; Left : Int64; Right : Int64; end record; + -- Return the width of RNG. + function Discrete_Range_Width (Rng : Discrete_Range_Type) return Width; + type Float_Range_Type is record Dir : Iir_Direction; Left : Fp64; @@ -95,6 +97,7 @@ package Synth.Values is type Rec_El_Array_Acc is access Rec_El_Array; type Type_Type (Kind : Type_Kind) is record + W : Width; case Kind is when Type_Bit => null; @@ -111,7 +114,6 @@ package Synth.Values is when Type_Unbounded_Array => Uarr_El : Type_Acc; when Type_Record => - Rec_W : Width; Rec : Rec_El_Array_Acc; end case; end record; @@ -210,7 +212,8 @@ package Synth.Values is Instance_Pool : Areapool_Acc; -- Types. - function Create_Discrete_Type (Rng : Discrete_Range_Type) return Type_Acc; + function Create_Discrete_Type (Rng : Discrete_Range_Type; W : Width) + return Type_Acc; function Create_Float_Type (Rng : Float_Range_Type) return Type_Acc; function Create_Vec_Type_By_Length (Len : Width; El : Type_Acc) return Type_Acc; |