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| author | Tristan Gingold <tgingold@free.fr> | 2020-04-15 07:35:24 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2020-04-15 07:36:01 +0200 |
| commit | 15539c0af43cc63d99239e3b65d936955cde3226 (patch) | |
| tree | 97e95dcd9f260a3a7acf2cf48dde556416a65ecd /src/synth/synth-stmts.adb | |
| parent | add25cf10b6886bfea9b2392e08142cee1698fd0 (diff) | |
| download | ghdl-15539c0af43cc63d99239e3b65d936955cde3226.tar.gz ghdl-15539c0af43cc63d99239e3b65d936955cde3226.tar.bz2 ghdl-15539c0af43cc63d99239e3b65d936955cde3226.zip | |
synth: rework edge handling to properly support falling edge. Fix #1227
Diffstat (limited to 'src/synth/synth-stmts.adb')
| -rw-r--r-- | src/synth/synth-stmts.adb | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/src/synth/synth-stmts.adb b/src/synth/synth-stmts.adb index e1d25384b..d994bc0ff 100644 --- a/src/synth/synth-stmts.adb +++ b/src/synth/synth-stmts.adb @@ -2934,14 +2934,12 @@ package body Synth.Stmts is -- Check the clock is an edge and extract it. Clk_Inst := Get_Net_Parent (Clk); - if Get_Id (Clk_Inst) /= Id_Edge then + if Get_Id (Clk_Inst) not in Edge_Module_Id then Error_Msg_Synth (+Stmt, "clock is not an edge"); Next_States := No_Net; return; end if; - Clk := Get_Input_Net (Clk_Inst, 0); - -- build idff States := Build_Idff (Build_Context, Clk, No_Net, Init); |