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| author | Tristan Gingold <tgingold@free.fr> | 2019-11-13 20:03:24 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-11-13 20:03:24 +0100 |
| commit | 559c6166f3c639330502f714babddb0bd6d986b4 (patch) | |
| tree | bc3b083ad90257af9b7d16d4948586a1028fec7d /src/synth/synth-static_oper.adb | |
| parent | 320a18c681edd29d8f58bd7f3109ae6ee1faffca (diff) | |
| download | ghdl-559c6166f3c639330502f714babddb0bd6d986b4.tar.gz ghdl-559c6166f3c639330502f714babddb0bd6d986b4.tar.bz2 ghdl-559c6166f3c639330502f714babddb0bd6d986b4.zip | |
synth: add some support for access types.
Diffstat (limited to 'src/synth/synth-static_oper.adb')
| -rw-r--r-- | src/synth/synth-static_oper.adb | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/synth/synth-static_oper.adb b/src/synth/synth-static_oper.adb index 4b301b128..c25775bae 100644 --- a/src/synth/synth-static_oper.adb +++ b/src/synth/synth-static_oper.adb @@ -188,6 +188,13 @@ package body Synth.Static_Oper is return Create_Value_Discrete (Boolean'Pos (not Is_Equal (Left, Right)), Boolean_Type); + when Iir_Predefined_Access_Equality => + return Create_Value_Discrete + (Boolean'Pos (Left.Acc = Right.Acc), Boolean_Type); + when Iir_Predefined_Access_Inequality => + return Create_Value_Discrete + (Boolean'Pos (Left.Acc /= Right.Acc), Boolean_Type); + when Iir_Predefined_Ieee_1164_Vector_And | Iir_Predefined_Ieee_Numeric_Std_And_Uns_Uns | Iir_Predefined_Ieee_Numeric_Std_And_Sgn_Sgn => |