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| author | Tristan Gingold <tgingold@free.fr> | 2019-09-08 08:00:42 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2019-09-11 06:37:27 +0200 |
| commit | 1e1eab735ecad00ee663a68e3a5118e041c20739 (patch) | |
| tree | 2fe36697581fd0b4e8499f3bacd2322a1cb53ae1 /src/synth/synth-context.adb | |
| parent | 67333b39047b444ea93f1efcabf7ea7b0371a972 (diff) | |
| download | ghdl-1e1eab735ecad00ee663a68e3a5118e041c20739.tar.gz ghdl-1e1eab735ecad00ee663a68e3a5118e041c20739.tar.bz2 ghdl-1e1eab735ecad00ee663a68e3a5118e041c20739.zip | |
synth: Add width field in type_type record.
Diffstat (limited to 'src/synth/synth-context.adb')
| -rw-r--r-- | src/synth/synth-context.adb | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/synth/synth-context.adb b/src/synth/synth-context.adb index d7af882b5..12ad60ed4 100644 --- a/src/synth/synth-context.adb +++ b/src/synth/synth-context.adb @@ -290,7 +290,7 @@ package body Synth.Context is Off := Off + 1; end; when Type_Discrete => - for I in reverse 0 .. Val.Typ.Drange.W - 1 loop + for I in reverse 0 .. Val.Typ.W - 1 loop declare B : constant Uns32 := Uns32 (Shift_Right (To_Uns64 (Val.Scal), Natural (I))) @@ -381,9 +381,9 @@ package body Synth.Context is Value2net (Val, 1, V, Res); return Res; end; - elsif Val.Typ.Drange.W <= 32 then + elsif Val.Typ.W <= 32 then return Build_Const_UB32 - (Build_Context, Uns32 (Val.Scal), Val.Typ.Drange.W); + (Build_Context, Uns32 (Val.Scal), Val.Typ.W); else raise Internal_Error; end if; |