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author | Tristan Gingold <tgingold@free.fr> | 2021-11-17 19:16:23 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-11-17 19:16:23 +0100 |
commit | 4ac40b32c52686bb2c84b640d25d71919cafdf0e (patch) | |
tree | 332e332120728538703eb9e4b06ccdba18fffcc6 /src/synth/netlists-memories.adb | |
parent | 4e1a1324b8ba4ef83f18742bd4a8588be94735fb (diff) | |
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synth/netlists-disp_verilog: display port attributes
Diffstat (limited to 'src/synth/netlists-memories.adb')
0 files changed, 0 insertions, 0 deletions