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authorTristan Gingold <tgingold@free.fr>2022-11-05 07:39:10 +0100
committerTristan Gingold <tgingold@free.fr>2022-11-05 08:01:05 +0100
commitb590278e3b9ef81ea940118a2eec41f2bc0e0380 (patch)
tree6867f56fe323c6b8d27947eb33c376ca774fcebe /src/synth/netlists-inference.adb
parente87e294be1f657f777ee39930c68bc02521ee74b (diff)
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synth: rework memory inference. Fix #2232
Diffstat (limited to 'src/synth/netlists-inference.adb')
-rw-r--r--src/synth/netlists-inference.adb76
1 files changed, 38 insertions, 38 deletions
diff --git a/src/synth/netlists-inference.adb b/src/synth/netlists-inference.adb
index 4504a462a..07bfddc9b 100644
--- a/src/synth/netlists-inference.adb
+++ b/src/synth/netlists-inference.adb
@@ -361,7 +361,7 @@ package body Netlists.Inference is
and then Can_Infere_RAM (Data, Prev_Val)
then
-- Maybe it is a RAM.
- Res := Infere_RAM (Ctxt, Data, Els_Net, Clk, Clk_Enable);
+ Ndata := Infere_RAM (Ctxt, Data, Els_Net, No_Net, Clk_Enable);
else
if Clk_Enable /= No_Net then
-- If there is a condition with the clock, that's an enable which
@@ -378,56 +378,56 @@ package body Netlists.Inference is
else
Ndata := Data;
end if;
+ end if;
- -- Create the FF.
- if Rst = No_Net then
- -- No async reset
- pragma Assert (Rst_Val = No_Net);
-
- if Els_Net /= No_Net then
- Els_Inst := Get_Net_Parent (Els_Net);
- if Get_Id (Els_Inst) in Dff_Module_Id
- and then Same_Clock (Clk, Get_Input_Net (Els_Inst, 0))
- then
- Els_Net := No_Net;
- end if;
+ -- Create the FF.
+ if Rst = No_Net then
+ -- No async reset
+ pragma Assert (Rst_Val = No_Net);
+
+ if Els_Net /= No_Net then
+ Els_Inst := Get_Net_Parent (Els_Net);
+ if Get_Id (Els_Inst) in Dff_Module_Id
+ and then Same_Clock (Clk, Get_Input_Net (Els_Inst, 0))
+ then
+ Els_Net := No_Net;
end if;
+ end if;
- if Els_Net = No_Net then
- if Init /= No_Net
- and then Get_Id (Get_Net_Parent (Init)) /= Id_Const_X
- then
- Res := Build_Idff (Ctxt, Clk, D => Ndata, Init => Init);
- else
- Res := Build_Dff (Ctxt, Clk, D => Ndata);
- end if;
+ if Els_Net = No_Net then
+ if Init /= No_Net
+ and then Get_Id (Get_Net_Parent (Init)) /= Id_Const_X
+ then
+ Res := Build_Idff (Ctxt, Clk, D => Ndata, Init => Init);
else
- if Init /= No_Net then
- Res := Build_Midff (Ctxt, Clk, D => Ndata,
- Els => Els_Net, Init => Init);
- else
- Res := Build_Mdff (Ctxt, Clk, D => Ndata, Els => Els_Net);
- end if;
+ Res := Build_Dff (Ctxt, Clk, D => Ndata);
end if;
else
- if Els_Net /= No_Net then
- Error_Msg_Netlist
- (Loc, "synchronous code does not expect else part");
- end if;
-
if Init /= No_Net then
- Res := Build_Iadff (Ctxt, Clk, D => Ndata,
- Rst => Rst, Rst_Val => Rst_Val,
- Init => Init);
+ Res := Build_Midff (Ctxt, Clk, D => Ndata,
+ Els => Els_Net, Init => Init);
else
- Res := Build_Adff (Ctxt, Clk, D => Ndata,
- Rst => Rst, Rst_Val => Rst_Val);
+ Res := Build_Mdff (Ctxt, Clk, D => Ndata, Els => Els_Net);
end if;
end if;
+ else
+ if Els_Net /= No_Net then
+ Error_Msg_Netlist
+ (Loc, "synchronous code does not expect else part");
+ end if;
- Set_Location (Res, Loc);
+ if Init /= No_Net then
+ Res := Build_Iadff (Ctxt, Clk, D => Ndata,
+ Rst => Rst, Rst_Val => Rst_Val,
+ Init => Init);
+ else
+ Res := Build_Adff (Ctxt, Clk, D => Ndata,
+ Rst => Rst, Rst_Val => Rst_Val);
+ end if;
end if;
+ Set_Location (Res, Loc);
+
-- The output may already be used (if the target is a variable that
-- is read). So redirect the net.
Redirect_Inputs (Get_Output (Last_Mux, 0), Res);