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author | Tristan Gingold <tgingold@free.fr> | 2023-01-03 13:53:37 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-01-03 16:47:28 +0100 |
commit | 1e5f96642bbf470934f245c98908337f75abb35a (patch) | |
tree | 32c6a26b31a4e27e7306ac7c9faa7159d65010a9 /src/synth/elab-vhdl_types.adb | |
parent | d7ffe048ed623283655a11ffc5e75d6e5731f738 (diff) | |
download | ghdl-1e5f96642bbf470934f245c98908337f75abb35a.tar.gz ghdl-1e5f96642bbf470934f245c98908337f75abb35a.tar.bz2 ghdl-1e5f96642bbf470934f245c98908337f75abb35a.zip |
synth: introduce type_array_unbounded
Diffstat (limited to 'src/synth/elab-vhdl_types.adb')
-rw-r--r-- | src/synth/elab-vhdl_types.adb | 27 |
1 files changed, 18 insertions, 9 deletions
diff --git a/src/synth/elab-vhdl_types.adb b/src/synth/elab-vhdl_types.adb index 9c80453b9..782de6b5e 100644 --- a/src/synth/elab-vhdl_types.adb +++ b/src/synth/elab-vhdl_types.adb @@ -566,14 +566,10 @@ package body Elab.Vhdl_Types is (Syn_Inst, Get_Array_Element (Parent_Typ), El_Type); else El_Typ := Parent_Typ; - loop - if Is_Last_Dimension (El_Typ) then - El_Typ := Get_Array_Element (El_Typ); - exit; - else - El_Typ := Get_Array_Element (El_Typ); - end if; + while not Is_Last_Dimension (El_Typ) loop + El_Typ := Get_Array_Element (El_Typ); end loop; + El_Typ := Get_Array_Element (El_Typ); end if; if not Get_Index_Constraint_Flag (Atype) then @@ -602,6 +598,7 @@ package body Elab.Vhdl_Types is -- FIXME: partially constrained arrays, subtype in indexes... if Get_Index_Constraint_Flag (Atype) then declare + El_Bounded : constant Boolean := Is_Bounded_Type (El_Typ); Res_Typ : Type_Acc; Bnd : Bound_Type; begin @@ -609,8 +606,13 @@ package body Elab.Vhdl_Types is for I in reverse Flist_First .. Flist_Last (St_Indexes) loop St_El := Get_Index_Type (St_Indexes, I); Bnd := Synth_Bounds_From_Range (Syn_Inst, St_El); - Res_Typ := Create_Array_Type - (Bnd, Res_Typ = El_Typ, Res_Typ); + if El_Bounded then + Res_Typ := Create_Array_Type + (Bnd, Res_Typ = El_Typ, Res_Typ); + else + Res_Typ := Create_Array_Unbounded_Type + (Bnd, Res_Typ = El_Typ, Res_Typ); + end if; end loop; return Res_Typ; end; @@ -618,6 +620,13 @@ package body Elab.Vhdl_Types is return Create_Unbounded_Array (Parent_Typ.Uarr_Idx, Parent_Typ.Ulast, El_Typ); end if; + when Type_Array_Unbounded => + if Is_Bounded_Type (El_Typ) then + return Create_Array_From_Array_Unbounded + (Parent_Typ, El_Typ); + else + raise Internal_Error; + end if; when Type_Vector | Type_Array => -- An alias with just a different resolver ? |