diff options
| author | Tristan Gingold <tgingold@free.fr> | 2016-07-18 07:01:04 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-07-18 07:01:04 +0200 |
| commit | afaf45e1da10e91cbab6856b1b97203b9f7c7e99 (patch) | |
| tree | 8a1dcfd0b047ea55af91ed4e51c73c9cd4103212 /src/std_names.ads | |
| parent | 2fd5fb225f89eb06e7b01f1fdbcee4be7241bd47 (diff) | |
| download | ghdl-afaf45e1da10e91cbab6856b1b97203b9f7c7e99.tar.gz ghdl-afaf45e1da10e91cbab6856b1b97203b9f7c7e99.tar.bz2 ghdl-afaf45e1da10e91cbab6856b1b97203b9f7c7e99.zip | |
Improve error message if synopsys package it not found.
Diffstat (limited to 'src/std_names.ads')
| -rw-r--r-- | src/std_names.ads | 29 |
1 files changed, 16 insertions, 13 deletions
diff --git a/src/std_names.ads b/src/std_names.ads index d830499a6..b63762072 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -469,19 +469,22 @@ package Std_Names is Name_Control_Simulation : constant Name_Id := Name_First_Misc + 026; Name_Last_Misc : constant Name_Id := Name_Control_Simulation; - Name_First_Ieee : constant Name_Id := Name_Last_Misc + 1; - Name_Ieee : constant Name_Id := Name_First_Ieee + 000; - Name_Std_Logic_1164 : constant Name_Id := Name_First_Ieee + 001; - Name_Std_Ulogic : constant Name_Id := Name_First_Ieee + 002; - Name_Std_Ulogic_Vector : constant Name_Id := Name_First_Ieee + 003; - Name_Std_Logic : constant Name_Id := Name_First_Ieee + 004; - Name_Std_Logic_Vector : constant Name_Id := Name_First_Ieee + 005; - Name_Rising_Edge : constant Name_Id := Name_First_Ieee + 006; - Name_Falling_Edge : constant Name_Id := Name_First_Ieee + 007; - Name_VITAL_Timing : constant Name_Id := Name_First_Ieee + 008; - Name_VITAL_Level0 : constant Name_Id := Name_First_Ieee + 009; - Name_VITAL_Level1 : constant Name_Id := Name_First_Ieee + 010; - Name_Last_Ieee : constant Name_Id := Name_VITAL_Level1; + Name_First_Ieee : constant Name_Id := Name_Last_Misc + 1; + Name_Ieee : constant Name_Id := Name_First_Ieee + 000; + Name_Std_Logic_1164 : constant Name_Id := Name_First_Ieee + 001; + Name_Std_Ulogic : constant Name_Id := Name_First_Ieee + 002; + Name_Std_Ulogic_Vector : constant Name_Id := Name_First_Ieee + 003; + Name_Std_Logic : constant Name_Id := Name_First_Ieee + 004; + Name_Std_Logic_Vector : constant Name_Id := Name_First_Ieee + 005; + Name_Rising_Edge : constant Name_Id := Name_First_Ieee + 006; + Name_Falling_Edge : constant Name_Id := Name_First_Ieee + 007; + Name_VITAL_Timing : constant Name_Id := Name_First_Ieee + 008; + Name_VITAL_Level0 : constant Name_Id := Name_First_Ieee + 009; + Name_VITAL_Level1 : constant Name_Id := Name_First_Ieee + 010; + Name_Std_Logic_Arith : constant Name_Id := Name_First_Ieee + 011; + Name_Std_Logic_Signed : constant Name_Id := Name_First_Ieee + 012; + Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 013; + Name_Last_Ieee : constant Name_Id := Name_Std_Logic_Unsigned; -- Verilog keywords. Name_First_Verilog : constant Name_Id := Name_Last_Ieee + 1; |