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| author | Tristan Gingold <tgingold@free.fr> | 2016-08-27 11:09:47 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2016-08-27 11:09:47 +0200 |
| commit | ae0b49dd52a354b2a37408641d7247fe9e7ef164 (patch) | |
| tree | db406763d6141300a6b7fecb4fab9a53f1a9f5de /src/std_names.ads | |
| parent | c5ef498aeeb6eb7ebd2ba998940986a119ce3f09 (diff) | |
| download | ghdl-ae0b49dd52a354b2a37408641d7247fe9e7ef164.tar.gz ghdl-ae0b49dd52a354b2a37408641d7247fe9e7ef164.tar.bz2 ghdl-ae0b49dd52a354b2a37408641d7247fe9e7ef164.zip | |
Display a nice message if std_logic_textio is not found.
Diffstat (limited to 'src/std_names.ads')
| -rw-r--r-- | src/std_names.ads | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/src/std_names.ads b/src/std_names.ads index b63762072..431a8c7dd 100644 --- a/src/std_names.ads +++ b/src/std_names.ads @@ -483,7 +483,8 @@ package Std_Names is Name_VITAL_Level1 : constant Name_Id := Name_First_Ieee + 010; Name_Std_Logic_Arith : constant Name_Id := Name_First_Ieee + 011; Name_Std_Logic_Signed : constant Name_Id := Name_First_Ieee + 012; - Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 013; + Name_Std_Logic_Textio : constant Name_Id := Name_First_Ieee + 013; + Name_Std_Logic_Unsigned : constant Name_Id := Name_First_Ieee + 014; Name_Last_Ieee : constant Name_Id := Name_Std_Logic_Unsigned; -- Verilog keywords. |