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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-09 19:05:40 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-10 07:48:51 +0100 |
| commit | 7286838d5caaa764c7201c82fe390483ef5c5661 (patch) | |
| tree | f920c3bea4ad69c91468e52fb724d396c3696062 /src/simul/simul-vhdl_elab.adb | |
| parent | 94166c9a2cdef18cdb3da9797d77ddd156c070b8 (diff) | |
| download | ghdl-7286838d5caaa764c7201c82fe390483ef5c5661.tar.gz ghdl-7286838d5caaa764c7201c82fe390483ef5c5661.tar.bz2 ghdl-7286838d5caaa764c7201c82fe390483ef5c5661.zip | |
synth-vhdl_aggr: optimize common aggregate
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 849553d01..423862f6e 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -157,12 +157,14 @@ package body Simul.Vhdl_Elab is if E.Kind in Mode_Signal_User then if E.Typ.W > 0 then - E.Nbr_Sources := - new Nbr_Sources_Array'(0 .. E.Typ.W - 1 => - (Nbr_Drivers => 0, - Nbr_Conns => 0, - Total => 0, - Last_Proc => No_Process_Index)); + E.Nbr_Sources := new Nbr_Sources_Array (0 .. E.Typ.W - 1); + -- Avoid aggregate to avoid stack overflow. + for I in E.Nbr_Sources'Range loop + E.Nbr_Sources (I) := (Nbr_Drivers => 0, + Nbr_Conns => 0, + Total => 0, + Last_Proc => No_Process_Index); + end loop; Mark_Resolved_Signals (0, Get_Type (E.Decl), E.Typ, E.Nbr_Sources.all, False); |