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| author | Tristan Gingold <tgingold@free.fr> | 2022-10-14 06:43:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-10-14 06:43:09 +0200 |
| commit | 690ad01b53efc31610a97992cbdc8efb1e03e155 (patch) | |
| tree | d62397d2190c4c8279bc4fa0d485818f42a03527 /src/simul/simul-vhdl_elab.adb | |
| parent | e74bc58708a296f809cf629d6e3ac15def3ada8a (diff) | |
| download | ghdl-690ad01b53efc31610a97992cbdc8efb1e03e155.tar.gz ghdl-690ad01b53efc31610a97992cbdc8efb1e03e155.tar.bz2 ghdl-690ad01b53efc31610a97992cbdc8efb1e03e155.zip | |
simul: handle delayed attribute
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 52f98817b..bdc6bdf9b 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -360,6 +360,17 @@ package body Simul.Vhdl_Elab is No_Sensitivity_Index, No_Signal_Index, No_Connect_Index, T, Pfx)); end; + when Iir_Kind_Delayed_Attribute => + declare + T : Std_Time; + Pfx : Sub_Signal_Type; + begin + T := Compute_Attribute_Time (Inst, Decl); + Pfx := Compute_Sub_Signal (Inst, Get_Prefix (Decl)); + Gather_Signal ((Mode_Delayed, Decl, Inst, null, null, null, + No_Sensitivity_Index, No_Signal_Index, + No_Connect_Index, T, Pfx)); + end; when Iir_Kind_Object_Alias_Declaration => -- In case it aliases a signal. declare |