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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-07 13:34:19 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-09 06:40:11 +0100 |
| commit | 2bdb325cc263b2d0ee4f7147cf168c0b0058d0f2 (patch) | |
| tree | 7fcb9b3de17fd41d26fefe551b86776cdfe504c2 /src/simul/simul-vhdl_elab.adb | |
| parent | 8f4b226dd33e46421ed307dbac0cef1e4f6c8489 (diff) | |
| download | ghdl-2bdb325cc263b2d0ee4f7147cf168c0b0058d0f2.tar.gz ghdl-2bdb325cc263b2d0ee4f7147cf168c0b0058d0f2.tar.bz2 ghdl-2bdb325cc263b2d0ee4f7147cf168c0b0058d0f2.zip | |
simul: handle PSL cover
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
| -rw-r--r-- | src/simul/simul-vhdl_elab.adb | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 8480432a6..77f3bc0b3 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -618,7 +618,8 @@ package body Simul.Vhdl_Elab is Gather_Sensitivity (Inst, Proc_Idx, List); return; end if; - when Iir_Kind_Psl_Assert_Directive => + when Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Cover_Directive => List := Get_PSL_Clock_Sensitivity (Proc); Gather_Sensitivity (Inst, Proc_Idx, List); return; @@ -903,9 +904,11 @@ package body Simul.Vhdl_Elab is Gather_Process_Drivers (Inst, Stmt, Processes_Table.Last); pragma Assert (Is_Expr_Pool_Empty); Gather_Process_Sensitivity (Inst, Stmt, Processes_Table.Last); - when Iir_Kind_Psl_Default_Clock => + when Iir_Kind_Psl_Default_Clock + | Iir_Kind_Psl_Declaration => null; when Iir_Kind_Psl_Assert_Directive + | Iir_Kind_Psl_Cover_Directive | Iir_Kind_Concurrent_Break_Statement => Processes_Table.Append ((Proc => Stmt, Inst => Inst, |