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author | Tristan Gingold <tgingold@free.fr> | 2022-12-26 09:25:00 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-12-26 10:25:21 +0100 |
commit | 1be382f13fe7d6b94dffec14922012fd463d4d04 (patch) | |
tree | e0c14b8777f8d0802564a3a4cd58151e5492d8e5 /src/simul/simul-vhdl_elab.adb | |
parent | ec534f56b3dfe5b4dbfae63303bc0c23ce68d4eb (diff) | |
download | ghdl-1be382f13fe7d6b94dffec14922012fd463d4d04.tar.gz ghdl-1be382f13fe7d6b94dffec14922012fd463d4d04.tar.bz2 ghdl-1be382f13fe7d6b94dffec14922012fd463d4d04.zip |
simul: handle transaction attribute
Diffstat (limited to 'src/simul/simul-vhdl_elab.adb')
-rw-r--r-- | src/simul/simul-vhdl_elab.adb | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/simul/simul-vhdl_elab.adb b/src/simul/simul-vhdl_elab.adb index 5c41511d6..36bc1df23 100644 --- a/src/simul/simul-vhdl_elab.adb +++ b/src/simul/simul-vhdl_elab.adb @@ -360,6 +360,15 @@ package body Simul.Vhdl_Elab is No_Sensitivity_Index, No_Signal_Index, No_Connect_Index, T, Pfx)); end; + when Iir_Kind_Transaction_Attribute => + declare + Pfx : Sub_Signal_Type; + begin + Pfx := Compute_Sub_Signal (Inst, Get_Prefix (Decl)); + Gather_Signal ((Mode_Transaction, Decl, Inst, null, null, null, + No_Sensitivity_Index, No_Signal_Index, + No_Connect_Index, 0, Pfx)); + end; when Iir_Kind_Delayed_Attribute => declare T : Std_Time; |