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| author | Tristan Gingold <tgingold@free.fr> | 2014-11-29 10:15:37 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2014-11-29 10:15:37 +0100 |
| commit | f75810293f0b1d43ba7492fd774a75ee7872584e (patch) | |
| tree | 05e941ef4e7eb95743a9f0e8277f3b6efc48eee4 /src/grt/grt-vcd.ads | |
| parent | 3046834bd44cde0c05ff49eecbd76d3b98401119 (diff) | |
| download | ghdl-f75810293f0b1d43ba7492fd774a75ee7872584e.tar.gz ghdl-f75810293f0b1d43ba7492fd774a75ee7872584e.tar.bz2 ghdl-f75810293f0b1d43ba7492fd774a75ee7872584e.zip | |
Initial support of FST dump format.
Diffstat (limited to 'src/grt/grt-vcd.ads')
| -rw-r--r-- | src/grt/grt-vcd.ads | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/grt/grt-vcd.ads b/src/grt/grt-vcd.ads index ed015af80..73096c5dd 100644 --- a/src/grt/grt-vcd.ads +++ b/src/grt/grt-vcd.ads @@ -47,7 +47,9 @@ package Grt.Vcd is type Vcd_Value_Kind is (Vcd_Effective, Vcd_Driving); type Verilog_Wire_Info is record + -- Signal address Addr : Address; + Irange : Ghdl_Range_Ptr; Kind : Vcd_Var_Kind; Val : Vcd_Value_Kind; |