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author | Tristan Gingold <tgingold@free.fr> | 2022-09-10 09:47:02 +0200 |
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committer | Tristan Gingold <tgingold@free.fr> | 2022-09-10 18:45:58 +0200 |
commit | ff1ef30e8d370f89294e2d6e82fb1a15cdcd519c (patch) | |
tree | 5e6184d1e4c3220a2d2f006027c0f9cf5b4af45f /src/ghdldrv | |
parent | 3d50ceb1772ec529ed168579d3d0b5603df96493 (diff) | |
download | ghdl-ff1ef30e8d370f89294e2d6e82fb1a15cdcd519c.tar.gz ghdl-ff1ef30e8d370f89294e2d6e82fb1a15cdcd519c.tar.bz2 ghdl-ff1ef30e8d370f89294e2d6e82fb1a15cdcd519c.zip |
synth: fix and add checks for memory management.
Diffstat (limited to 'src/ghdldrv')
-rw-r--r-- | src/ghdldrv/ghdlsynth.adb | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index 138dca8df..9a70bc912 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -49,6 +49,7 @@ with Netlists.Rename; with Elab.Vhdl_Context; use Elab.Vhdl_Context; with Elab.Vhdl_Insts; with Elab.Debugger; +with Elab.Vhdl_Objtypes; with Synthesis; with Synth.Disp_Vhdl; @@ -465,6 +466,7 @@ package body Ghdlsynth is return Module is use Vhdl.Configuration; + use Elab.Vhdl_Objtypes; Args : Argument_List (1 .. Argc); Res : Module; Cmd : Command_Synth; @@ -499,11 +501,15 @@ package body Ghdlsynth is Inst := Elab.Vhdl_Insts.Elab_Top_Unit (Get_Library_Unit (Config)); + pragma Assert (Is_Expr_Pool_Empty); + Res := Synthesis.Synth_Design (Config, Inst, Cmd.Top_Encoding); if Res = No_Module then return No_Module; end if; + pragma Assert (Is_Expr_Pool_Empty); + Disp_Design (Cmd, Format_None, Res, Config, Inst); -- De-elaborate all packages, so that they could be re-used for @@ -514,6 +520,8 @@ package body Ghdlsynth is end loop; Set_Elab_Flag (Vhdl.Std_Package.Std_Standard_Unit, False); + pragma Assert (Is_Expr_Pool_Empty); + Vhdl.Annotations.Finalize_Annotate; Synth.Vhdl_Context.Free_Base_Instance; return Res; |