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| author | Tristan Gingold <tgingold@free.fr> | 2022-08-18 06:21:17 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2022-08-18 06:21:17 +0200 |
| commit | fe6edccd9c03f40878cc1d27b07c024407d63bff (patch) | |
| tree | 556c0f25e5179b112f1209e6f07dbfe9bd9b1d5c /src/ghdldrv | |
| parent | 0db659f0d91d57c5b36ae40c3be0f542a4ad75d1 (diff) | |
| download | ghdl-fe6edccd9c03f40878cc1d27b07c024407d63bff.tar.gz ghdl-fe6edccd9c03f40878cc1d27b07c024407d63bff.tar.bz2 ghdl-fe6edccd9c03f40878cc1d27b07c024407d63bff.zip | |
ghdlsimul: add an option to debug before elaboration
Diffstat (limited to 'src/ghdldrv')
| -rw-r--r-- | src/ghdldrv/ghdlsimul.adb | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb index ae8a6d4b4..a2c1d3ca2 100644 --- a/src/ghdldrv/ghdlsimul.adb +++ b/src/ghdldrv/ghdlsimul.adb @@ -179,6 +179,8 @@ package body Ghdlsimul is Synth.Flags.Flag_Trace_Statements := True; elsif Option = "-i" then Simul.Vhdl_Simul.Flag_Interractive := True; + elsif Option = "-ge" then + Simul.Vhdl_Simul.Flag_Debug_Elab := True; else return False; end if; |