synth: rename vhdl.annotations to elab.vhdl_annotations

2 files changed, 6 insertions, 5 deletions

diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb
index 94d7c0e97..03322c54a 100644
--- a/src/ghdldrv/ghdlsimul.adb
+++ b/src/ghdldrv/ghdlsimul.adb
@@ -31,7 +31,8 @@ with Errorout;
 with Vhdl.Nodes; use Vhdl.Nodes;
 with Vhdl.Std_Package;
 with Vhdl.Canon;
-with Vhdl.Annotations;
+
+with Elab.Vhdl_Annotations;
 
 with Grt.Options;
 with Grt.Types;
@@ -66,7 +67,7 @@ package body Ghdlsimul is
       Vhdl.Canon.Canon_Flag_Add_Labels := True;
       Vhdl.Canon.Canon_Flag_Add_Suspend_State := True;
 
-      Vhdl.Annotations.Flag_Synthesis := True;
+      Elab.Vhdl_Annotations.Flag_Synthesis := True;
 
       --  Do not canon concurrent statements.
       Vhdl.Canon.Canon_Flag_Concurrent_Stmts := False;
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb
index 9a70bc912..711ad66bc 100644
--- a/src/ghdldrv/ghdlsynth.adb
+++ b/src/ghdldrv/ghdlsynth.adb
@@ -35,7 +35,6 @@ with Vhdl.Scanner;
 with Vhdl.Std_Package;
 with Vhdl.Canon;
 with Vhdl.Configuration;
-with Vhdl.Annotations;
 with Vhdl.Utils;
 
 with Netlists.Dump;
@@ -46,6 +45,7 @@ with Netlists.Errors;
 with Netlists.Inference;
 with Netlists.Rename;
 
+with Elab.Vhdl_Annotations;
 with Elab.Vhdl_Context; use Elab.Vhdl_Context;
 with Elab.Vhdl_Insts;
 with Elab.Debugger;
@@ -264,7 +264,7 @@ package body Ghdlsynth is
    procedure Synth_Compile_Init (Enable_Translate_Off : Boolean;
                                  Load_Work : Boolean) is
    begin
-      Vhdl.Annotations.Flag_Synthesis := True;
+      Elab.Vhdl_Annotations.Flag_Synthesis := True;
       if Enable_Translate_Off then
          Vhdl.Scanner.Flag_Comment_Keyword := True;
          Vhdl.Scanner.Flag_Pragma_Comment := True;
@@ -522,7 +522,7 @@ package body Ghdlsynth is
 
       pragma Assert (Is_Expr_Pool_Empty);
 
-      Vhdl.Annotations.Finalize_Annotate;
+      Elab.Vhdl_Annotations.Finalize_Annotate;
       Synth.Vhdl_Context.Free_Base_Instance;
       return Res;