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| author | Tristan Gingold <tgingold@free.fr> | 2023-01-31 18:57:14 +0100 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2023-01-31 20:27:01 +0100 |
| commit | 919cc95cce51bbe0fb1fb0778ed63fffd184977b (patch) | |
| tree | 6aaee65fb0ca7b73adbdb999b8fc32a61046969a /src/ghdldrv | |
| parent | eaf29d1c2491419a0e9b51e2866c329f60892613 (diff) | |
| download | ghdl-919cc95cce51bbe0fb1fb0778ed63fffd184977b.tar.gz ghdl-919cc95cce51bbe0fb1fb0778ed63fffd184977b.tar.bz2 ghdl-919cc95cce51bbe0fb1fb0778ed63fffd184977b.zip | |
ghdlsimul: extract simul-main from simul-vhdl_simul
Diffstat (limited to 'src/ghdldrv')
| -rw-r--r-- | src/ghdldrv/ghdlsimul.adb | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb index a1f315678..475b19204 100644 --- a/src/ghdldrv/ghdlsimul.adb +++ b/src/ghdldrv/ghdlsimul.adb @@ -53,8 +53,10 @@ with Elab.Debugger; with Synth.Flags; with Synth.Errors; with Synth.Vhdl_Foreign; + with Simul.Vhdl_Elab; with Simul.Vhdl_Simul; +with Simul.Main; package body Ghdlsimul is procedure Compile_Init (Analyze_Only : Boolean) is @@ -234,9 +236,9 @@ package body Ghdlsimul is elsif Option = "-t" then Synth.Flags.Flag_Trace_Statements := True; elsif Option = "-i" then - Simul.Vhdl_Simul.Flag_Interractive := True; + Simul.Main.Flag_Interractive := True; elsif Option = "-ge" then - Simul.Vhdl_Simul.Flag_Debug_Elab := True; + Simul.Main.Flag_Debug_Elab := True; elsif Option'Last > 3 and then Option (Option'First + 1) = 'g' and then Is_Generic_Override_Option (Option) |