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author | Tristan Gingold <tgingold@free.fr> | 2023-01-16 18:53:59 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2023-01-16 18:53:59 +0100 |
commit | 288021722ffbc7eb2a01549d08bbd04584da5c75 (patch) | |
tree | bf8afc0b4be6e4ac37ff1775667ede0592264ef1 /src/ghdldrv | |
parent | f261c1390eacb1c2af6c613c01c4c03d461db5de (diff) | |
download | ghdl-288021722ffbc7eb2a01549d08bbd04584da5c75.tar.gz ghdl-288021722ffbc7eb2a01549d08bbd04584da5c75.tar.bz2 ghdl-288021722ffbc7eb2a01549d08bbd04584da5c75.zip |
ghdlsimul: check foreign subprograms
Diffstat (limited to 'src/ghdldrv')
-rw-r--r-- | src/ghdldrv/ghdlsimul.adb | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/src/ghdldrv/ghdlsimul.adb b/src/ghdldrv/ghdlsimul.adb index bb76bab24..909253e60 100644 --- a/src/ghdldrv/ghdlsimul.adb +++ b/src/ghdldrv/ghdlsimul.adb @@ -35,6 +35,7 @@ with Vhdl.Sem; with Vhdl.Canon; with Vhdl.Configuration; with Vhdl.Utils; +with Vhdl.Back_End; with Grt.Options; with Grt.Types; @@ -58,13 +59,13 @@ package body Ghdlsimul is procedure Compile_Init (Analyze_Only : Boolean) is begin Common_Compile_Init (Analyze_Only); + + Vhdl.Back_End.Sem_Foreign := Vhdl.Back_End.Sem_Foreign_Wrapper'Access; + if Analyze_Only then return; end if; - -- FIXME: add a flag to force unnesting. - -- Translation.Flag_Unnest_Subprograms := True; - -- The design is always analyzed in whole. Flags.Flag_Whole_Analyze := True; Vhdl.Canon.Canon_Flag_Add_Labels := True; |