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author | Tristan Gingold <tgingold@free.fr> | 2021-11-28 10:50:31 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2021-11-28 12:13:27 +0100 |
commit | 852b1e064f81c7c7108c45847872a266e995d31c (patch) | |
tree | 8b20cf943d4359850c64d118ed3ab884cd24090c /src/ghdldrv/ghdlsynth.adb | |
parent | bbdc99ad0bdca7d327f8d8167f38461e6900be41 (diff) | |
download | ghdl-852b1e064f81c7c7108c45847872a266e995d31c.tar.gz ghdl-852b1e064f81c7c7108c45847872a266e995d31c.tar.bz2 ghdl-852b1e064f81c7c7108c45847872a266e995d31c.zip |
synth: adjustments for foreign_module
Diffstat (limited to 'src/ghdldrv/ghdlsynth.adb')
-rw-r--r-- | src/ghdldrv/ghdlsynth.adb | 13 |
1 files changed, 10 insertions, 3 deletions
diff --git a/src/ghdldrv/ghdlsynth.adb b/src/ghdldrv/ghdlsynth.adb index 229edcb1b..669588132 100644 --- a/src/ghdldrv/ghdlsynth.adb +++ b/src/ghdldrv/ghdlsynth.adb @@ -375,7 +375,7 @@ package body Ghdlsynth is Foreign_Resolve_Instances.all; end if; - if Get_Kind (Config) = Iir_Kind_Design_Unit then + if Get_Kind (Get_Library_Unit (Config)) /= Iir_Kind_Foreign_Module then -- Check (and possibly abandon) if entity can be at the top of the -- hierarchy. declare @@ -421,7 +421,8 @@ package body Ghdlsynth is when Format_Dot => Netlists.Disp_Dot.Disp_Dot_Top_Module (Res); when Format_Vhdl => - if Get_Kind (Config) = Iir_Kind_Foreign_Module then + if Get_Kind (Get_Library_Unit (Config)) = Iir_Kind_Foreign_Module + then -- Not a VHDL design. Netlists.Disp_Vhdl.Disp_Vhdl (Res); else @@ -506,6 +507,7 @@ package body Ghdlsynth is Res : Module; Inst : Synth_Instance_Acc; Config : Iir; + Lib_Unit : Iir; begin Config := Ghdl_Synth_Configure (True, Cmd, Args); @@ -517,7 +519,12 @@ package body Ghdlsynth is end if; end if; - Inst := Elab.Vhdl_Insts.Elab_Top_Unit (Get_Library_Unit (Config)); + Lib_Unit := Get_Library_Unit (Config); + if Get_Kind (Lib_Unit) /= Iir_Kind_Foreign_Module then + Inst := Elab.Vhdl_Insts.Elab_Top_Unit (Lib_Unit); + else + Inst := null; + end if; if Errorout.Nbr_Errors > 0 then Res := No_Module; |