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| author | Tristan Gingold <tgingold@free.fr> | 2014-09-25 07:38:09 +0200 |
|---|---|---|
| committer | Tristan Gingold <tgingold@free.fr> | 2014-09-25 07:38:09 +0200 |
| commit | 68d26922e31aad3cb34dd3b7689bcec75ad70fcb (patch) | |
| tree | ed7d40115bd74b0c4216a94bfc21d5af0837ce4f /simulate/simulation.adb | |
| parent | 5edf93b87e8f3528d9063df08bf70bf538d72545 (diff) | |
| download | ghdl-68d26922e31aad3cb34dd3b7689bcec75ad70fcb.tar.gz ghdl-68d26922e31aad3cb34dd3b7689bcec75ad70fcb.tar.bz2 ghdl-68d26922e31aad3cb34dd3b7689bcec75ad70fcb.zip | |
Add a python script to automatically generate disp_tree.
Diffstat (limited to 'simulate/simulation.adb')
| -rw-r--r-- | simulate/simulation.adb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/simulate/simulation.adb b/simulate/simulation.adb index d951324fc..3f3f8715b 100644 --- a/simulate/simulation.adb +++ b/simulate/simulation.adb @@ -1246,7 +1246,7 @@ package body Simulation is is pragma Unreferenced (Formal_Instance); Formal : constant Iir := Get_Formal (Assoc); - Inter : constant Iir := Get_Base_Name (Formal); + Inter : constant Iir := Get_Association_Interface (Assoc); begin if False and Trace_Elaboration then Put ("connect formal "); |