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author | Tristan Gingold <tgingold@free.fr> | 2013-12-17 06:25:53 +0100 |
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committer | Tristan Gingold <tgingold@free.fr> | 2013-12-17 06:25:53 +0100 |
commit | 48448a12ef628218db298d8b7c6879e28cdd019a (patch) | |
tree | 7e612d41dc01c435cf32e3cee029b429c9362bb9 /sem_stmts.adb | |
parent | 04ad1cd54d99fc3ac3d82c69ee5f7c2db7e2275a (diff) | |
download | ghdl-48448a12ef628218db298d8b7c6879e28cdd019a.tar.gz ghdl-48448a12ef628218db298d8b7c6879e28cdd019a.tar.bz2 ghdl-48448a12ef628218db298d8b7c6879e28cdd019a.zip |
Sync tree: add parsing of AMS-VHDL, add Darwin syntax in asm files.
Diffstat (limited to 'sem_stmts.adb')
-rw-r--r-- | sem_stmts.adb | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/sem_stmts.adb b/sem_stmts.adb index b5a8f17e6..373ea7d68 100644 --- a/sem_stmts.adb +++ b/sem_stmts.adb @@ -1702,6 +1702,31 @@ package body Sem_Stmts is Sem_Guard (Stmt); end Sem_Concurrent_Selected_Signal_Assignment; + procedure Simple_Simultaneous_Statement (Stmt : Iir) is + Left, Right : Iir; + Res_Type : Iir; + begin + Left := Get_Simultaneous_Left (Stmt); + Right := Get_Simultaneous_Right (Stmt); + + Left := Sem_Expression_Ov (Left, Null_Iir); + Right := Sem_Expression_Ov (Right, Null_Iir); + + -- Give up in case of error + if Left = Null_Iir or else Right = Null_Iir then + return; + end if; + + Res_Type := Search_Compatible_Type (Get_Type (Left), Get_Type (Right)); + if Res_Type = Null_Iir then + Error_Msg_Sem ("types of left and right expressions are incompatible", + Stmt); + return; + end if; + + -- FIXME: check for nature type... + end Simple_Simultaneous_Statement; + procedure Sem_Concurrent_Statement_Chain (Parent : Iir; Is_Passive : Boolean) is @@ -1776,6 +1801,8 @@ package body Sem_Stmts is Sem_Psl.Sem_Psl_Assert_Statement (El); when Iir_Kind_Psl_Default_Clock => Sem_Psl.Sem_Psl_Default_Clock (El); + when Iir_Kind_Simple_Simultaneous_Statement => + Simple_Simultaneous_Statement (El); when others => Error_Kind ("sem_concurrent_statement_chain", El); end case; |